Patents by Inventor Chia-Wen Wang

Chia-Wen Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11152338
    Abstract: A method includes forming a stacked structure of a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked in a first direction over a substrate, the first semiconductor layers being thicker than the second semiconductor layers. The method also includes patterning the stacked structure into a first fin structure and a second fin structure extending along a second direction substantially perpendicular to the first direction. The method further includes removing the first semiconductor layers of the first fin structure to form a plurality of nanowires. Each of the nanowires has a first height, there is a distance between two adjacent nanowires along the vertical direction, and the distance is greater than the first height. The method includes forming a first gate structure between the second semiconductor layers of the first fin structure.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhi-Qiang Wu, Chun-Fu Cheng, Chung-Cheng Wu, Yi-Han Wang, Chia-Wen Liu
  • Patent number: 11146273
    Abstract: The present invention provides an electronic device including a wireless communication module, a counter and a processing circuit. The wireless communication module is configured to receive a first packet and a second packet from another electronic device, wherein the first packet includes a first counter value, the second packet includes a second counter value, and the first counter value and the second counter value correspond to two adjacent edges of an original signal of another electronic device, respectively. The processing circuit is configured to obtain a third counter value from the counter when the first packet is received, and obtain a fourth counter value from the counter when the second packet is received; and the processing circuit further generates an output signal that is substantially the same as the original signal according to the first counter value, the second counter value, the third counter value and the fourth counter value.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: October 12, 2021
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chia-Chun Hung, Chih-Wei Ho, Chin-Wen Wang, Liang-Hui Li, Yi-Cheng Chen
  • Publication number: 20210297105
    Abstract: The present disclosure provides a protection case assembly for a handheld device. The protection case assembly includes a main case and a frame. The main case has an accommodating space configured to accommodate the handheld device, and an opening disposed correspondingly to a lens module of the handheld device. The frame is detachably disposed in the opening, and includes a groove set configured to receive the main case in the opening.
    Type: Application
    Filed: July 13, 2020
    Publication date: September 23, 2021
    Inventors: CHING-FU WANG, SHENG-CHE SU, PO-WEN HSIAO, CHIA-HO LIN
  • Patent number: 11121308
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a magnetoresistive random access memory (MRAM) cell over a substrate. A dielectric structure overlies the substrate. The MRAM cell is disposed within the dielectric structure. The MRAM cell includes a magnetic tunnel junction (MTJ) sandwiched between a bottom electrode and a top electrode. A conductive wire overlies the top electrode. A sidewall spacer structure continuously extends along a sidewall of the MTJ and the top electrode. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first and second sidewall spacer layers. The first and second sidewall spacer layers comprise a first material and the protective sidewall spacer layer comprises a second material different than the first material.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Wen Chang, Chung-Chiang Min, Harry-Hak-Lay Chuang, Hung Cho Wang, Tsung-Hsueh Yang, Yuan-Tai Tseng, Sheng-Huang Huang, Chia-Hua Lin
  • Patent number: 11107293
    Abstract: A head mounted display system includes a scanning unit and a processing unit. The scanning unit is configured to scan a real object in a real environment so as to generate a scanning result. The processing unit is coupled to the scanning unit. The processing unit is configured to identify the real object according to the scanning result of the scanning unit, determine at least one predetermined interactive characteristic according to an identification result of the processing unit, create a virtual object in a virtual environment corresponding to the real object in the real environment according to the scanning result of the scanning unit, and assign the at least one predetermined interactive characteristic to the virtual object in the virtual environment. Therefore, the present disclosure allows a user to manipulate the virtual object in different ways more naturally, which effectively improves the user's interactive experience.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: August 31, 2021
    Assignee: XRSpace CO., LTD.
    Inventors: Chih-Wen Wang, Chia-Ming Lu, Feng-Seng Chu, Wei-Shuo Chen
  • Publication number: 20210265998
    Abstract: The present invention provides an electronic device including a wireless communication module, a counter and a processing circuit. The wireless communication module is configured to receive a first packet and a second packet from another electronic device, wherein the first packet includes a first counter value, the second packet includes a second counter value, and the first counter value and the second counter value correspond to two adjacent edges of an original signal of another electronic device, respectively. The processing circuit is configured to obtain a third counter value from the counter when the first packet is received, and obtain a fourth counter value from the counter when the second packet is received; and the processing circuit further generates an output signal that is substantially the same as the original signal according to the first counter value, the second counter value, the third counter value and the fourth counter value.
    Type: Application
    Filed: February 22, 2021
    Publication date: August 26, 2021
    Inventors: Chia-Chun Hung, Chih-Wei Ho, Chin-Wen Wang, Liang-Hui Li, Yi-Cheng Chen
  • Publication number: 20210217866
    Abstract: A non-volatile memory device includes a substrate. A plurality of shallow trench isolation (STI) lines are disposed on the substrate and extend along a first direction. A memory gate structure is disposed on the substrate between adjacent two of the plurality of STI lines. A trench line is disposed in the substrate and extends along a second direction intersecting the first direction, wherein the trench line also crosses top portions of the plurality of STI lines. A conductive line is disposed in the trench line and used as a selection line to be coupled to the memory gate structure.
    Type: Application
    Filed: February 18, 2020
    Publication date: July 15, 2021
    Applicant: United Microelectronics Corp.
    Inventors: Chia-Wen Wang, Chien-Hung Chen, Chia-Hui Huang, Jen Yang Hsueh, Ling Hsiu Chou, Chih-Yang Hsu
  • Patent number: 10720440
    Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: July 21, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Wen Wang, Hsiang-Chen Lee, Wen-Peng Hsu, Kuo-Lung Li, Meng-Chun Chen, Zi-Jun Liu, Ping-Chia Shih
  • Publication number: 20190043877
    Abstract: A non-volatile memory device includes a semiconductor substrate, a control gate electrode, a first oxide-nitride-oxide (ONO) structure, a selecting gate electrode, a second ONO structure, and a spacer structure. The control gate electrode and the selecting gate electrode are disposed on the semiconductor substrate. The first ONO structure is disposed between the control gate electrode and the semiconductor substrate. The second ONO structure is disposed between the control gate electrode and the selecting gate electrode in a first direction. The spacer structure is disposed between the control gate electrode and the second ONO structure in the first direction. A distance between the control gate electrode and the selecting gate electrode in the first direction is smaller than or equal to a sum of a width of the second ONO structure and a width of the spacer structure in the first direction.
    Type: Application
    Filed: August 1, 2017
    Publication date: February 7, 2019
    Inventors: Kuo-Lung Li, Ping-Chia Shih, Wen-Peng Hsu, Chia-Wen Wang, Meng-Chun Chen, Chih-Hao Pan
  • Patent number: 10199385
    Abstract: A non-volatile memory device includes a semiconductor substrate, a control gate electrode, a first oxide-nitride-oxide (ONO) structure, a selecting gate electrode, a second ONO structure, and a spacer structure. The control gate electrode and the selecting gate electrode are disposed on the semiconductor substrate. The first ONO structure is disposed between the control gate electrode and the semiconductor substrate. The second ONO structure is disposed between the control gate electrode and the selecting gate electrode in a first direction. The spacer structure is disposed between the control gate electrode and the second ONO structure in the first direction. A distance between the control gate electrode and the selecting gate electrode in the first direction is smaller than or equal to a sum of a width of the second ONO structure and a width of the spacer structure in the first direction.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: February 5, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Lung Li, Ping-Chia Shih, Wen-Peng Hsu, Chia-Wen Wang, Meng-Chun Chen, Chih-Hao Pan
  • Publication number: 20180211966
    Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.
    Type: Application
    Filed: March 21, 2018
    Publication date: July 26, 2018
    Applicant: United Microelectronics Corp.
    Inventors: Chia-Wen Wang, Hsiang-Chen Lee, Wen-Peng Hsu, Kuo-Lung Li, Meng-Chun Chen, Zi-Jun Liu, Ping-Chia Shih
  • Patent number: 9966382
    Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: May 8, 2018
    Assignee: United Microelectronics Corp.
    Inventors: Chia-Wen Wang, Hsiang-Chen Lee, Wen-Peng Hsu, Kuo-Lung Li, Meng-Chun Chen, Zi-Jun Liu, Ping-Chia Shih
  • Publication number: 20180053771
    Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.
    Type: Application
    Filed: August 16, 2016
    Publication date: February 22, 2018
    Applicant: United Microelectronics Corp.
    Inventors: Chia-Wen Wang, Hsiang-Chen Lee, Wen-Peng Hsu, Kuo-Lung Li, Meng-Chun Chen, Zi-Jun Liu, Ping-Chia Shih
  • Patent number: 9466497
    Abstract: The invention provides a method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory cell, comprising: (S1) forming a pad oxide pattern on a silicon substrate having a recess exposing a tunnel region of the silicon substrate; (S2) forming a bottom oxide layer, a nitride layer, a top oxide layer covering the recess and the pad oxide pattern to form a first ONO structure; (S3) forming a photoresist on the first ONO structure covering the recess and a peripheral region of the pad oxide pattern; (S4) removing a part of the first ONO structure exposed by the photoresist to form an U-shaped ONO structure; (S5) trimming the photoresist to exposed a part of the U-shaped ONO structure above the recess; (S6) removing the part of the U-shaped ONO structure; (S7) removing the photoresist; (S8) removing the pad oxide pattern and the top oxide layer; and (S9) forming a gate structure.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: October 11, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Kuo-Lung Li, Ping-Chia Shih, Hsiang-Chen Lee, Yu-Chun Chang, Chia-Wen Wang, Meng-Chun Chen, Chih-Yang Hsu
  • Patent number: RE38830
    Type: Grant
    Filed: January 23, 2002
    Date of Patent: October 18, 2005
    Assignee: Industrial Technology Research Institute
    Inventors: Chia-Wen Wang, Yu-Lin Chao, Jeng-Yeong Tyan
  • Patent number: D464044
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: October 8, 2002
    Assignee: Industrial Technology Research Institute
    Inventors: Chia-Wen Wang, Yu-Lin Chao, Cheng-Yeh Yang
  • Patent number: D402978
    Type: Grant
    Filed: January 28, 1998
    Date of Patent: December 22, 1998
    Assignee: Industrial Technology Research Institute
    Inventors: Chia-Wen Wang, Yu-Lin Chao, Jeng-Yeong Tyan
  • Patent number: D420676
    Type: Grant
    Filed: December 30, 1998
    Date of Patent: February 15, 2000
    Assignee: Industrial Technology Research Institute
    Inventors: Chia-Wen Wang, Ching-Lung Chan