Patents by Inventor Chia-Wen Wang

Chia-Wen Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250110307
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Application
    Filed: December 12, 2024
    Publication date: April 3, 2025
    Inventors: Chao-Chang HU, Chih-Wei WENG, Chia-Che WU, Chien-Yu KAO, Hsiao-Hsin HU, He-Ling CHANG, Chao-Hsi WANG, Chen-Hsien FAN, Che-Wei CHANG, Mao-Gen JIAN, Sung-Mao TSAI, Wei-Jhe SHEN, Yung-Ping YANG, Sin-Hong LIN, Tzu-Yu CHANG, Sin-Jhong SONG, Shang-Yu HSU, Meng-Ting LIN, Shih-Wei HUNG, Yu-Huai LIAO, Mao-Kuo HSU, Hsueh-Ju LU, Ching-Chieh HUANG, Chih-Wen CHIANG, Yu-Chiao LO, Ying-Jen WANG, Shu-Shan CHEN, Che-Hsiang CHIU
  • Publication number: 20250113488
    Abstract: Provided are a memory structure and a manufacturing method thereof. The memory structure includes a substrate having first and second regions, first and second isolation structures in the substrate, a charge storage layer on the substrate, first and second gates and doped regions. The first isolation structures define first active areas in the first region. A top surface of the first isolation structure is higher than that of the substrate. The second isolation structures define second active areas in the second region. A top surface of the second isolation structure is lower than that of the substrate. The first gate is on the charge storage layer in the first active area. The second gate is on the charge storage layer in the second active area. The doped regions are in the substrate at two sides of the first gate and at two sides of the second gate.
    Type: Application
    Filed: October 25, 2023
    Publication date: April 3, 2025
    Applicant: United Microelectronics Corp.
    Inventors: Chia-Wen Wang, Chien-Hung Chen, Chia-Hui Huang, Ling Hsiu Chou, Jen Yang Hsueh, Chih-Yang Hsu
  • Publication number: 20250112049
    Abstract: Implementations described herein provide a method of forming a semiconductor device. The method includes forming a nanostructure having a first set of layers of a first material and a second set of layers, alternating with the first set of layers, having a second material. The method further includes depositing a hard mask on a top layer of the first set of layers, the hard mask including a first hard mask layer on the top layer of the first set of layers and a second hard mask layer on the first hard mask layer. The method also includes depositing elements of a cladding structure on sidewalls of the nanostructure and the hard mask. The method further includes removing a top portion of the cladding structure. The method further includes removing the second hard mask layer after removing the top portion of the cladding structure.
    Type: Application
    Filed: December 12, 2024
    Publication date: April 3, 2025
    Inventors: Chia-Cheng CHAO, Hsin-Chieh HUANG, Yu-Wen WANG
  • Patent number: 12266703
    Abstract: An interconnect fabrication method is disclosed herein that utilizes a disposable etch stop hard mask over a gate structure during source/drain contact formation and replaces the disposable etch stop hard mask with a dielectric feature (in some embodiments, dielectric layers having a lower dielectric constant than a dielectric constant of dielectric layers of the disposable etch stop hard mask) before gate contact formation. An exemplary device includes a contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion separated by a spacing and a dielectric feature disposed over a gate structure, where the dielectric feature and the gate structure fill the spacing between the first sidewall CESL portion and the second sidewall CESL portion. The dielectric feature includes a bulk dielectric over a dielectric liner. The dielectric liner separates the bulk dielectric from the gate structure and the CESL.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: April 1, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Che Lin, Po-Yu Huang, I-Wen Wu, Chen-Ming Lee, Chia-Hsien Yao, Chao-Hsun Wang, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 12253518
    Abstract: The present invention provides a magnetic-control measurement system, comprises a reaction container and a programable magnetron measurement unit.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: March 18, 2025
    Assignee: Chung Yuan Christian University
    Inventors: Tzong-Rong Ger, Hong-Siang Wang, Yu-Che Cheng, Hsing-Cheng Chu, Jing-Wen Tsai, Chia-Ke Tsou
  • Publication number: 20250085764
    Abstract: A method of performing power saving control on a display device includes: generating, by a timing controller of the display device, a power saving start indication and a power saving end indication in response to changing of a refresh rate of the display device; receiving, by a source driver of the display device, the power saving start indication and the power saving end indication; in response to the power saving start indication, allowing a part of circuitry of the source driver to be powered down during a vertical blanking interval; and in response to the power saving end indication, allowing the powered down part of circuitry of the source driver to be woken up during the vertical blanking interval.
    Type: Application
    Filed: September 7, 2023
    Publication date: March 13, 2025
    Applicant: HIMAX TECHNOLOGIES LIMITED
    Inventors: Hung-Yu Huang, Shu-Ming Chang, Chia-Hui Wang, Shiang-Wei Wang, Sheng-Wen Huang, Tsung-Yi Tsai
  • Patent number: 12248353
    Abstract: A method of performing power saving control on a display device includes: generating, by a timing controller of the display device, a power saving start indication and a power saving end indication in response to changing of a refresh rate of the display device; receiving, by a source driver of the display device, the power saving start indication and the power saving end indication; in response to the power saving start indication, allowing a part of circuitry of the source driver to be powered down during a vertical blanking interval; and in response to the power saving end indication, allowing the powered down part of circuitry of the source driver to be woken up during the vertical blanking interval.
    Type: Grant
    Filed: September 7, 2023
    Date of Patent: March 11, 2025
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Hung-Yu Huang, Shu-Ming Chang, Chia-Hui Wang, Shiang-Wei Wang, Sheng-Wen Huang, Tsung-Yi Tsai
  • Patent number: 12224209
    Abstract: A manufacturing method of a semiconductor device includes forming a stack of first semiconductor layers and second semiconductor layers alternatively formed on top of one another, where a topmost layer of the stack is one of the second semiconductor layers; forming a patterned mask layer on the topmost layer of the stack; forming a trench in the stack based on the patterned mask layer to form a fin structure; forming a cladding layer extending along sidewalls of the fin structure; and removing the patterned mask layer and a portion of the cladding layer by performing a two-step etching process, where the portion of the cladding layer is removed to form cladding spacers having a concave top surface with a recess depth increasing from the sidewalls of the fin structure.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: February 11, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chao, Hsin-Chieh Huang, Yu-Wen Wang
  • Publication number: 20250033173
    Abstract: A pneumatic puller includes a shell unit, a pulling member that has a fixed section and an exposed section, a piston that is fixedly connected to the fixed section, a directional valve assembly that is movably mounted to the piston, and a cylinder that is sleeved on the fixed section. The cylinder and the piston define a first chamber and a second chamber. The cylinder is movable along the fixed section between a first reverse position and a second reverse position relative to the piston when urged by pressure of a gas. The cylinder abuts against one side of the piston and the directional valve assembly releases the gas into the second chamber when the cylinder is in the first reverse position. The cylinder moves along the fixed section away from the exposed section and hits the piston when moving from the first reverse position to the second reverse position.
    Type: Application
    Filed: July 24, 2024
    Publication date: January 30, 2025
    Applicant: BASSO INDUSTRY CORP.
    Inventors: Chun-Chi LAI, Chia-Wen WANG
  • Patent number: 12205822
    Abstract: Implementations described herein provide a method of forming a semiconductor device. The method includes forming a nanostructure having a first set of layers of a first material and a second set of layers, alternating with the first set of layers, having a second material. The method further includes depositing a hard mask on a top layer of the first set of layers, the hard mask including a first hard mask layer on the top layer of the first set of layers and a second hard mask layer on the first hard mask layer. The method also includes depositing elements of a cladding structure on sidewalls of the nanostructure and the hard mask. The method further includes removing a top portion of the cladding structure. The method further includes removing the second hard mask layer after removing the top portion of the cladding structure.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: January 21, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chao, Hsin-Chieh Huang, Yu-Wen Wang
  • Patent number: 12204163
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: February 5, 2024
    Date of Patent: January 21, 2025
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Patent number: 12119053
    Abstract: When programming an MLC memory device, the disturb characteristics of a program block having multiple memory cells are measured, and the threshold voltage variations of the multiple memory cells are then acquired based on the disturb characteristics of the program block. Next, multiple initial program voltage pulses are provided according to a predetermined signal level, and multiple compensated program voltage pulses are provided by adjusting the multiple initial program voltage pulses. Last, the multiple compensated program voltage pulses are outputted to the program block for programming the multiple memory cells to the predetermined signal level.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: October 15, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Wen Wang, Chien-Hung Chen, Chia-Hui Huang, Jen-Yang Hsueh, Ling-Hsiu Chou, Chih-Yang Hsu
  • Publication number: 20240114688
    Abstract: A memory structure including a substrate, a first doped region, a second doped region, a first gate, a second gate, a first charge storage structure, and a second charge storage structure is provided. The first gate is located on the first doped region. The second gate is located on the second doped region. The first charge storage structure is located between the first gate and the first doped region. The first charge storage structure includes a first tunneling dielectric layer, a first dielectric layer, and a first charge storage layer. The second charge storage structure is located between the second gate and the second doped region. The second charge storage structure includes a second tunneling dielectric layer, a second dielectric layer, and a second charge storage layer. The thickness of the second tunneling dielectric layer is greater than the thickness of the first tunneling dielectric layer.
    Type: Application
    Filed: November 21, 2022
    Publication date: April 4, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Chia-Wen Wang, Chien-Hung Chen, Chia-Hui Huang, Ling Hsiu Chou, Jen Yang Hsueh, Chih-Yang Hsu
  • Patent number: 11825657
    Abstract: A semiconductor device includes a substrate having thereon at least one active area and at least one trench isolation region adjacent to the at least one active area. A charge trapping structure is disposed on the at least one active area and at least one trench isolation region. At least one divot is disposed in the at least one trench isolation region adjacent to the charge trapping structure. A silicon oxide layer is disposed in the at least one divot. A gate oxide layer is disposed on the at least one active area around the charge trapping structure.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: November 21, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chia-Wen Wang
  • Publication number: 20230238058
    Abstract: When programming an MLC memory device, the disturb characteristics of a program block having multiple memory cells are measured, and the threshold voltage variations of the multiple memory cells are then acquired based on the disturb characteristics of the program block. Next, multiple initial program voltage pulses are provided according to a predetermined signal level, and multiple compensated program voltage pulses are provided by adjusting the multiple initial program voltage pulses. Last, the multiple compensated program voltage pulses are outputted to the program block for programming the multiple memory cells to the predetermined signal level.
    Type: Application
    Filed: February 24, 2022
    Publication date: July 27, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Wen Wang, Chien-Hung Chen, Chia-Hui Huang, Jen-Yang Hsueh, Ling-Hsiu Chou, Chih-Yang Hsu
  • Patent number: 11532716
    Abstract: A non-volatile memory device includes a substrate. A plurality of shallow trench isolation (STI) lines are disposed on the substrate and extend along a first direction. A memory gate structure is disposed on the substrate between adjacent two of the plurality of STI lines. A trench line is disposed in the substrate and extends along a second direction intersecting the first direction, wherein the trench line also crosses top portions of the plurality of STI lines. A conductive line is disposed in the trench line and used as a selection line to be coupled to the memory gate structure.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: December 20, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Wen Wang, Chien-Hung Chen, Chia-Hui Huang, Jen Yang Hsueh, Ling Hsiu Chou, Chih-Yang Hsu
  • Publication number: 20220278123
    Abstract: A semiconductor device includes a substrate having thereon at least one active area and at least one trench isolation region adjacent to the at least one active area. A charge trapping structure is disposed on the at least one active area and at least one trench isolation region. At least one divot is disposed in the at least one trench isolation region adjacent to the charge trapping structure. A silicon oxide layer is disposed in the at least one divot. A gate oxide layer is disposed on the at least one active area around the charge trapping structure.
    Type: Application
    Filed: March 22, 2022
    Publication date: September 1, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventor: Chia-Wen Wang
  • Patent number: 11362102
    Abstract: A semiconductor device includes a substrate having thereon at least one active area and at least one trench isolation region adjacent to the at least one active area. A charge trapping structure is disposed on the at least one active area and at least one trench isolation region. At least one divot is disposed in the at least one trench isolation region adjacent to the charge trapping structure. A silicon oxide layer is disposed in the at least one divot. A gate oxide layer is disposed on the at least one active area around the charge trapping structure.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: June 14, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chia-Wen Wang
  • Publication number: 20210217866
    Abstract: A non-volatile memory device includes a substrate. A plurality of shallow trench isolation (STI) lines are disposed on the substrate and extend along a first direction. A memory gate structure is disposed on the substrate between adjacent two of the plurality of STI lines. A trench line is disposed in the substrate and extends along a second direction intersecting the first direction, wherein the trench line also crosses top portions of the plurality of STI lines. A conductive line is disposed in the trench line and used as a selection line to be coupled to the memory gate structure.
    Type: Application
    Filed: February 18, 2020
    Publication date: July 15, 2021
    Applicant: United Microelectronics Corp.
    Inventors: Chia-Wen Wang, Chien-Hung Chen, Chia-Hui Huang, Jen Yang Hsueh, Ling Hsiu Chou, Chih-Yang Hsu
  • Patent number: 10720440
    Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: July 21, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Wen Wang, Hsiang-Chen Lee, Wen-Peng Hsu, Kuo-Lung Li, Meng-Chun Chen, Zi-Jun Liu, Ping-Chia Shih