Abstract: A channel hiatus correction method for an HDMI device is provided. A recovery code from scrambled data of the stream is obtained. A liner feedback shift register (LFSR) value of channels of the HDMI port is obtained based on the recovery code and the scrambled data of the stream. The stream is de-scrambled according to the LFSR value of the channels of the HDMI port. Video data is displayed according to the de-scrambled stream.

Abstract: A memory structure including a substrate, a first doped region, a second doped region, a first gate, a second gate, a first charge storage structure, and a second charge storage structure is provided. The first gate is located on the first doped region. The second gate is located on the second doped region. The first charge storage structure is located between the first gate and the first doped region. The first charge storage structure includes a first tunneling dielectric layer, a first dielectric layer, and a first charge storage layer. The second charge storage structure is located between the second gate and the second doped region. The second charge storage structure includes a second tunneling dielectric layer, a second dielectric layer, and a second charge storage layer. The thickness of the second tunneling dielectric layer is greater than the thickness of the first tunneling dielectric layer.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: A detection system and method for the migrating cell is provided. The system is configured to detect a migrating cell combined with an immunomagnetic bead. The system includes a platform, a microchannel, a magnetic field source, a coherent light source and an optical sensing module. The microchannel is configured to allow the migrating cell to flow in it along a flow direction. The magnetic field source is configured to provide magnetic force to the migrating cell combined with the immunomagnetic bead. The magnetic force includes at least one magnetic force component and the magnetic force component is opposite to the flow direction of the microchannel. The coherent light source is configured to provide the microchannel with the coherent light. The optical sensing module is configured to receive the interference light caused by the coherent light being reflected by the sample inside the microchannel.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor fin. The semiconductor device includes first spacers over the semiconductor fin. The semiconductor device includes a metal gate structure, over the semiconductor fin, that is sandwiched at least by the first spacers. The semiconductor device includes a gate electrode contacting the metal gate structure. An interface between the metal gate structure and the gate electrode has its side portions extending toward the semiconductor fin with a first distance and a central portion extending toward the semiconductor fin with a second distance, the first distance being substantially less than the second distance.

Abstract: A semiconductor device includes a substrate having thereon at least one active area and at least one trench isolation region adjacent to the at least one active area. A charge trapping structure is disposed on the at least one active area and at least one trench isolation region. At least one divot is disposed in the at least one trench isolation region adjacent to the charge trapping structure. A silicon oxide layer is disposed in the at least one divot. A gate oxide layer is disposed on the at least one active area around the charge trapping structure.

Abstract: When programming an MLC memory device, the disturb characteristics of a program block having multiple memory cells are measured, and the threshold voltage variations of the multiple memory cells are then acquired based on the disturb characteristics of the program block. Next, multiple initial program voltage pulses are provided according to a predetermined signal level, and multiple compensated program voltage pulses are provided by adjusting the multiple initial program voltage pulses. Last, the multiple compensated program voltage pulses are outputted to the program block for programming the multiple memory cells to the predetermined signal level.

Abstract: A non-volatile memory device includes a substrate. A plurality of shallow trench isolation (STI) lines are disposed on the substrate and extend along a first direction. A memory gate structure is disposed on the substrate between adjacent two of the plurality of STI lines. A trench line is disposed in the substrate and extends along a second direction intersecting the first direction, wherein the trench line also crosses top portions of the plurality of STI lines. A conductive line is disposed in the trench line and used as a selection line to be coupled to the memory gate structure.

Abstract: A semiconductor device includes a substrate having thereon at least one active area and at least one trench isolation region adjacent to the at least one active area. A charge trapping structure is disposed on the at least one active area and at least one trench isolation region. At least one divot is disposed in the at least one trench isolation region adjacent to the charge trapping structure. A silicon oxide layer is disposed in the at least one divot. A gate oxide layer is disposed on the at least one active area around the charge trapping structure.

Abstract: A semiconductor device includes a substrate having thereon at least one active area and at least one trench isolation region adjacent to the at least one active area. A charge trapping structure is disposed on the at least one active area and at least one trench isolation region. At least one divot is disposed in the at least one trench isolation region adjacent to the charge trapping structure. A silicon oxide layer is disposed in the at least one divot. A gate oxide layer is disposed on the at least one active area around the charge trapping structure.

Abstract: A non-volatile memory device includes a substrate. A plurality of shallow trench isolation (STI) lines are disposed on the substrate and extend along a first direction. A memory gate structure is disposed on the substrate between adjacent two of the plurality of STI lines. A trench line is disposed in the substrate and extends along a second direction intersecting the first direction, wherein the trench line also crosses top portions of the plurality of STI lines. A conductive line is disposed in the trench line and used as a selection line to be coupled to the memory gate structure.

Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.

Abstract: A non-volatile memory device includes a semiconductor substrate, a control gate electrode, a first oxide-nitride-oxide (ONO) structure, a selecting gate electrode, a second ONO structure, and a spacer structure. The control gate electrode and the selecting gate electrode are disposed on the semiconductor substrate. The first ONO structure is disposed between the control gate electrode and the semiconductor substrate. The second ONO structure is disposed between the control gate electrode and the selecting gate electrode in a first direction. The spacer structure is disposed between the control gate electrode and the second ONO structure in the first direction. A distance between the control gate electrode and the selecting gate electrode in the first direction is smaller than or equal to a sum of a width of the second ONO structure and a width of the spacer structure in the first direction.

Abstract: A non-volatile memory device includes a semiconductor substrate, a control gate electrode, a first oxide-nitride-oxide (ONO) structure, a selecting gate electrode, a second ONO structure, and a spacer structure. The control gate electrode and the selecting gate electrode are disposed on the semiconductor substrate. The first ONO structure is disposed between the control gate electrode and the semiconductor substrate. The second ONO structure is disposed between the control gate electrode and the selecting gate electrode in a first direction. The spacer structure is disposed between the control gate electrode and the second ONO structure in the first direction. A distance between the control gate electrode and the selecting gate electrode in the first direction is smaller than or equal to a sum of a width of the second ONO structure and a width of the spacer structure in the first direction.

Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.

Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.

Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.

Abstract: The invention provides a method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory cell, comprising: (S1) forming a pad oxide pattern on a silicon substrate having a recess exposing a tunnel region of the silicon substrate; (S2) forming a bottom oxide layer, a nitride layer, a top oxide layer covering the recess and the pad oxide pattern to form a first ONO structure; (S3) forming a photoresist on the first ONO structure covering the recess and a peripheral region of the pad oxide pattern; (S4) removing a part of the first ONO structure exposed by the photoresist to form an U-shaped ONO structure; (S5) trimming the photoresist to exposed a part of the U-shaped ONO structure above the recess; (S6) removing the part of the U-shaped ONO structure; (S7) removing the photoresist; (S8) removing the pad oxide pattern and the top oxide layer; and (S9) forming a gate structure.