Abstract: Some implementations described herein provide a semiconductor device and methods of formation. The semiconductor device includes a gate-all-around transistor having one or more dielectric regions that include or more dielectric gases. The dielectric regions may include a first dielectric region between epitaxial regions (e.g., source/drain regions) and a first portion of a gate structure of the gate-all-around transistor. The dielectric regions may further include a second dielectric region between a contact structure of gate-all-around transistor and a second portion of the gate structure. By including the dielectric regions in the gate-all-around transistor, a parasitic capacitance associated with the gate-all-around transistor may be reduced relative to another gate-all-around transistor not including the dielectric regions.

Abstract: A method of manufacturing an integrated circuit (IC) includes providing a structure having a fin over a substrate in a region of the IC, a sacrificial gate stack engaging a channel region of the fin, and gate spacers on sidewalls of the sacrificial gate stack. The first layers and the second layers are alternately stacked over the substrate. The method also includes etching the fin adjacent the gate spacers, resulting in source/drain trenches, partially recessing the second layers exposed in the source/drain trenches, resulting in gaps between adjacent layers of the first layers in the fin, depositing inner spacer features in the gaps in the fin, epitaxially growing source/drain features in the source/drain trenches, and replacing the sacrificial gate stack with a metal gate stack. The metal gate stack includes a gate dielectric layer disposed over top and sidewalls of the fin having both the first and the second layers.

Abstract: An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is on a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is on a backside of the source epitaxial structure and a backside of the drain epitaxial structure and has an air gap therein. The backside via extends through the backside dielectric layer to a first one of the source epitaxial structure and the drain epitaxial structure.

Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, which includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer, is formed. An isolation insulating layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer is formed. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer is recessed. A third dielectric layer is formed on the recessed second dielectric layer. The third dielectric layer is partially removed to form a trench. A fourth dielectric layer is formed by filling the trench with a dielectric material, thereby forming a wall fin structure.

Abstract: Embodiments utilize a two layer inner spacer structure during formation of the inner spacers of a nano-FET device. The materials of the first inner spacer layer and second inner spacer layer can be selected to have a mismatch in their coefficients of thermal expansion (CTE). As the structure cools after deposition, the inner spacer layer which has a larger CTE will exhibit compressive stress on the other inner spacer layer, however, because the two layers have a common interface, the layer with the smaller CTE will exhibit a counter acting tensile stress.

Abstract: A method is provided for forming an integrated circuit (IC) chip package structure. The method includes providing a substrate for an interposer, and forming a conductive interconnect structure in and on the substrate for connecting a group of selected IC dies. The method includes forming warpage-reducing trenches in non-routing regions of the interposer, wherein the warpage-reducing trenches are sized and positioned based on a warpage characteristic to reduce the warpage of the chip package structure. The method also includes depositing a warpage-relief material in the warpage-reducing trenches according to the warpage characteristic to reduce the warpage of the chip package structure, and bonding the group of selected IC dies to the interposer to form a chip package structure.

Abstract: A device a includes a substrate, two source/drain (S/D) features over the substrate, and semiconductor layers suspended over the substrate and connecting the two S/D features. The device further includes a dielectric layer disposed between two adjacent layers of the semiconductor layers and an air gap between the dielectric layer and one of the S/D features, where a ratio between a length of the air gap to a thickness of the first dielectric layer is in a range of 0.1 to 1.0.

Abstract: A method includes providing a fin extending from a substrate, the fin including a plurality of semiconductor channel layers, and where a gate is disposed over the fin. A first spacer layer is deposited over the gate and over the fin in a source/drain region. The first spacer layer has a first etch rate. A second spacer layer is deposited over the first spacer layer. The second spacer layer has a second etch rate less than the first etch rate. The plurality of semiconductor channel layers are removed from the source/drain region to form a trench having a funnel shape. After forming the trench, inner spacers are formed along a sidewall surface of the trench. In various embodiments, lateral sidewall surfaces of each semiconductor channel layer of the plurality of semiconductor channel layers is substantially free of an inner spacer material.

Abstract: An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is on a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is on a backside of the source epitaxial structure and a backside of the drain epitaxial structure and has an air gap therein. The backside via extends through the backside dielectric layer to a first one of the source epitaxial structure and the drain epitaxial structure.

Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.

Abstract: A method for manufacturing a semiconductor device includes forming a first dielectric layer over a semiconductor fin. The method includes forming a second dielectric layer over the first dielectric layer. The method includes exposing a portion of the first dielectric layer. The method includes oxidizing a surface of the second dielectric layer while limiting oxidation on the exposed portion of the first dielectric layer.

Abstract: A method for separating and transporting a glass sheet from a glass ribbon includes drawing the glass ribbon along a draw path in a conveyance direction, scoring the glass ribbon with a scoring device, to produce a score line across at least a portion of a width of the glass ribbon, engaging a first edge of the glass ribbon at a first position downstream of the score line in the conveyance direction with a first robotic handling device, engaging a second edge of the glass ribbon at a second position downstream of the score line in the conveyance direction with a second robotic handling device, and synchronously moving the first robotic handling device and the second robotic handling device to bend the glass ribbon about the score line and separate the glass sheet from the glass ribbon.

Abstract: A position-bias compensation method, applied to a three-dimensional image interactive system, includes steps of: displaying a three-dimensional image and setting a trigger position in a preset interactive coordinate system according to a default position of a user; obtaining a position-bias of a user's position from the default position; and resetting the trigger position according to the position-bias.

Abstract: A position-bias compensation method, applied to a three-dimensional image interactive system, includes steps of: displaying a three-dimensional image and setting a trigger position in a preset interactive coordinate system according to a default position of a user; obtaining a position-bias of a user's position from the default position; and resetting the trigger position according to the position-bias.