Abstract: A dynamic precharge redundant circuit for a semiconductor memory device. A PMOS transistor, a fuse, a first, second and third inverters, a first switch and a second switch are applied. A source of the PMOS transistor is coupled to a voltage supply, while a gate of the PMOS transistor is to receive a precharge signal. The fuse has a ground terminal and a terminal coupled to the drain of the PMOS transistor of which the drain is further coupled to an input terminal of the first inverter. The fuse is also coupled to a column address signal. The first inverter has an output terminal coupled to an input terminal of the first switch. The second inverter has an input terminal coupled to an output terminal of the first switch and an output terminal coupled to an input terminal of the third inverter, so as to output a bit-switch control signal.