Patents by Inventor Chia-Yin Chen

Chia-Yin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170011988
    Abstract: A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.
    Type: Application
    Filed: September 19, 2016
    Publication date: January 12, 2017
    Inventors: Yung-Chi Lin, Hsin-Yu Chen, Ming-Tsu Chung, HsiaoYun Lo, Hong-Ye Shih, Chia-Yin Chen, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 9449898
    Abstract: A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: September 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Hsin-Yu Chen, Ming-Tsu Chung, HsiaoYun Lo, Hong-Ye Shih, Chia-Yin Chen, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Publication number: 20160250879
    Abstract: A blanket for transferring a paste image from an engraved plate to a substrate is provided. The blanket includes a foam; a supporting layer on the foam; and a paste transfer layer on the supporting layer. The paste transfer layer is an inter-penetrating polymer network of silicone rubber and fluoroelastomer.
    Type: Application
    Filed: February 26, 2015
    Publication date: September 1, 2016
    Inventors: Chia-Yin CHEN, Chuan-Jen FU, Hsin-Jung LIN, Ruoh-Huey UANG
  • Patent number: 9269677
    Abstract: A packaging substrate and a semiconductor package using the packaging substrate are provided. The packaging substrate includes: a substrate body having a die attach area, a circuit layer formed around the die attach area and having a plurality of conductive traces each having a wire bonding pad, and a surface treatment layer formed on the wire bonding pads. Therein, only one of the conductive traces is connected to an electroplating line so as to prevent cross-talk that otherwise occurs between conductive traces due to too many electroplating lines in the prior art.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: February 23, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chia-Yin Chen, Yu-Ching Liu, Yueh-Chiung Chang, Yu-Po Wang
  • Publication number: 20150050782
    Abstract: A packaging substrate and a semiconductor package using the packaging substrate are provided. The packaging substrate includes: a substrate body having a die attach area, a circuit layer formed around the die attach area and having a plurality of conductive traces each having a wire bonding pad, and a surface treatment layer formed on the wire bonding pads. Therein, only one of the conductive traces is connected to an electroplating line so as to prevent cross-talk that otherwise occurs between conductive traces due to too many electroplating lines in the prior art.
    Type: Application
    Filed: November 3, 2014
    Publication date: February 19, 2015
    Inventors: Chia-Yin Chen, Yu-Ching Liu, Yueh-Chiung Chang, Yu-Po Wang
  • Publication number: 20150035159
    Abstract: A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.
    Type: Application
    Filed: July 31, 2013
    Publication date: February 5, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Hsin-Yu Chen, Ming-Tsu Chung, HsiaoYun Lo, Hong-Ye Shih, Chia-Yin Chen, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 8901729
    Abstract: A packaging substrate and a semiconductor package using the packaging substrate are provided. The packaging substrate includes: a substrate body having a die attach area, a circuit layer formed around the die attach area and having a plurality of conductive traces each having a wire bonding pad, and a surface treatment layer formed on the wire bonding pads. Therein, only one of the conductive traces is connected to an electroplating line so as to prevent cross-talk that otherwise occurs between conductive traces due to too many electroplating lines in the prior art.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: December 2, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chia-Yin Chen, Yu-Ching Liu, Yueh-Chiung Chang, Yu-Po Wang
  • Publication number: 20130161837
    Abstract: A packaging substrate and a semiconductor package using the packaging substrate are provided. The packaging substrate includes: a substrate body having a die attach area, a circuit layer formed around the die attach area and having a plurality of conductive traces each having a wire bonding pad, and a surface treatment layer formed on the wire bonding pads. Therein, only one of the conductive traces is connected to an electroplating line so as to prevent cross-talk that otherwise occurs between conductive traces due to too many electroplating lines in the prior art.
    Type: Application
    Filed: June 7, 2012
    Publication date: June 27, 2013
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chia-Yin Chen, Yu-Ching Liu, Yueh-Chiung Chang, Yu-Po Wang
  • Patent number: 4929728
    Abstract: A process for preparing 3-(1H-tetrazol-5-yl)-4(3H)-quinazolinone ammonium salts of the formula I: ##STR1## wherein: R is hydrogen, halogen, C.sub.1 -C.sub.3 alkyl or C.sub.1 -C.sub.3 alkoxy,which process comprises:reacting ethyl N-(1H-tetrazol-5-yl) formimidate in an inert solvent with substituted anthranilamide of the formula IV ##STR2## wherein R is as defined above. The process is simpler than prior processes for preparing the same compounds and thus is economically valuable.
    Type: Grant
    Filed: November 2, 1989
    Date of Patent: May 29, 1990
    Assignee: National Science Council
    Inventors: Ji-Wang Chern, Kang-Chien Liu, Chia-Yin Chen