Abstract: Embodiments of the present disclosure includes a semiconductor device. The semiconductor device includes first suspended nanostructures vertically stacked over one another and disposed on a substrate, a first gate stack engaging the first suspended nanostructures, a first gate spacer disposed on sidewalls of the first gate stack, second suspended nanostructures vertically stacked over one another and disposed on the substrate, a second gate stack engaging the second suspended nanostructures, and a second gate spacer disposed on sidewalls of the second gate stack. A middle portion of the first suspended nanostructures has a first thickness measured in a direction perpendicular to a top surface of the substrate. A middle portion of the second suspended nanostructures has a second thickness measured in the direction. The second thickness is smaller than the first thickness.

Abstract: Embodiments of the present disclosure includes a semiconductor device. The semiconductor device includes first suspended nanostructures vertically stacked over one another and disposed on a substrate, a first gate stack engaging the first suspended nanostructures, a first gate spacer disposed on sidewalls of the first gate stack, second suspended nanostructures vertically stacked over one another and disposed on the substrate, a second gate stack engaging the second suspended nanostructures, and a second gate spacer disposed on sidewalls of the second gate stack. A middle portion of the first suspended nanostructures has a first thickness measured in a direction perpendicular to a top surface of the substrate. A middle portion of the second suspended nanostructures has a second thickness measured in the direction. The second thickness is smaller than the first thickness.

Abstract: Embodiments of the present disclosure includes a method of forming a semiconductor device. The method includes providing a substrate having a plurality of first semiconductor layers and a plurality of second semiconductor layers disposed over the substrate. The method also includes patterning the first semiconductor layers and the second semiconductor layers to form a first fin and a second fin, removing the first semiconductor layers from the first and second fins such that a first portion of the patterned second semiconductor layers becomes first suspended nanostructures in the first fin and that a second portion of the patterned second semiconductor layers becomes second suspended nanostructures in the second fin, and doping a threshold modifying impurity into the first suspended nanostructures in the first fin.

Abstract: Embodiments relate to a semiconductor device structure including a first channel layer having a first surface and a second surface, a second channel layer having a first surface and a second surface, and the first and second channel layers are formed of a first material. The structure also includes a first dopant suppression layer in contact with the second surface of the first channel layer, and a second dopant suppression layer parallel to the first dopant suppression layer. The second dopant suppression layer is in contact with the first surface of the second channel layer, and the first and second dopant suppression layers each comprises carbon or fluorine. The structure further includes a gate dielectric layer in contact with the first and second dopant suppression layers and the first surface of the first channel layer, and a gate electrode layer disposed on the gate dielectric layer.

Abstract: Embodiments relate to a semiconductor device structure including a first channel layer having a first surface and a second surface, a second channel layer having a first surface and a second surface, and the first and second channel layers are formed of a first material. The structure also includes a first dopant suppression layer in contact with the second surface of the first channel layer, and a second dopant suppression layer parallel to the first dopant suppression layer. The second dopant suppression layer is in contact with the first surface of the second channel layer, and the first and second dopant suppression layers each comprises carbon or fluorine. The structure further includes a gate dielectric layer in contact with the first and second dopant suppression layers and the first surface of the first channel layer, and a gate electrode layer disposed on the gate dielectric layer.

Abstract: Embodiments relate to a semiconductor device structure including a first channel layer having a first surface and a second surface, a second channel layer having a first surface and a second surface, and the first and second channel layers are formed of a first material. The structure also includes a first dopant suppression layer in contact with the second surface of the first channel layer, and a second dopant suppression layer parallel to the first dopant suppression layer. The second dopant suppression layer is in contact with the first surface of the second channel layer, and the first and second dopant suppression layers each comprises carbon or fluorine. The structure further includes a gate dielectric layer in contact with the first and second dopant suppression layers and the first surface of the first channel layer, and a gate electrode layer disposed on the gate dielectric layer.

Abstract: Embodiments of the present disclosure includes a method of forming a semiconductor device. The method includes providing a substrate having a plurality of first semiconductor layers and a plurality of second semiconductor layers disposed over the substrate. The method also includes patterning the first semiconductor layers and the second semiconductor layers to form a first fin and a second fin, removing the first semiconductor layers from the first and second fins such that a first portion of the patterned second semiconductor layers becomes first suspended nanostructures in the first fin and that a second portion of the patterned second semiconductor layers becomes second suspended nanostructures in the second fin, and doping a threshold modifying impurity into the first suspended nanostructures in the first fin. The impurity causes transistors formed with the first fin and second fin have different threshold voltages.

Abstract: A semiconductor light-emitting device including a substrate, a first-type doped semiconductor structure, a light-emitting layer, and a second-type doped semiconductor layer is provided. The first-type doped semiconductor structure is located on the substrate and includes a base and multi-section rod structures extended upward from the base. Each multi-section rod structure includes rods and at least one connecting portion. The connecting portion connects adjacent rods along a first direction, wherein the first direction is perpendicular to the base and points to the connecting portion from the base. Cross-section areas of different rods on a reference plane parallel to the substrate are different, and cross-section areas of the connecting portion on the reference plane decrease along the first direction. The light-emitting layer is located on sidewalls of the rods. The second-type doped semiconductor layer is located on the light-emitting layer.

Abstract: A semiconductor device including a Si (110) substrate, a buffer layer, a first type doped semiconductor layer, a light-emitting layer and a second type doped semiconductor layer is provided. The Si (110) substrate has a plurality of trenches. Each trench at least extends along a first direction, and the first direction is parallel to a <1-10> crystal direction of the Si (110) substrate. The buffer layer is located on the Si (110) substrate and exposes the trenches. The first type doped semiconductor layer is located on the buffer layer and covers the trenches. The light-emitting layer is located on the first type doped semiconductor layer. The second type doped semiconductor layer is located on the light-emitting layer. A fabrication method of a semiconductor device is also provided.

Abstract: A semiconductor light-emitting device including a substrate, a first-type doped semiconductor structure, a light-emitting layer, and a second-type doped semiconductor layer is provided. The first-type doped semiconductor structure is located on the substrate and includes a base and multi-section rod structures extended upward from the base. Each multi-section rod structure includes rods and at least one connecting portion. The connecting portion connects adjacent rods along a first direction, wherein the first direction is perpendicular to the base and points to the connecting portion from the base. Cross-section areas of different rods on a reference plane parallel to the substrate are different, and cross-section areas of the connecting portion on the reference plane decrease along the first direction. The light-emitting layer is located on sidewalls of the rods. The second-type doped semiconductor layer is located on the light-emitting layer.

Abstract: A semiconductor device including a Si (110) substrate, a buffer layer, a first type doped semiconductor layer, a light-emitting layer and a second type doped semiconductor layer is provided. The Si (110) substrate has a plurality of trenches. Each trench at least extends along a first direction, and the first direction is parallel to a <1-10> crystal direction of the Si (110) substrate. The buffer layer is located on the Si (110) substrate and exposes the trenches. The first type doped semiconductor layer is located on the buffer layer and covers the trenches. The light-emitting layer is located on the first type doped semiconductor layer. The second type doped semiconductor layer is located on the light-emitting layer. A fabrication method of a semiconductor device is also provided.