Abstract: A double data rate (DDR) transmitter and a clock converter circuit are provided. The clock converter circuit includes a first logic circuit and a second logic circuit. The first logic circuit receives a clock signal as a trigger signal, performs a sequential logic operation based on the clock signal, and outputs a result of the sequential logic operation. The second logic circuit is coupled to the first logic circuit. The second logic circuit performs a combinational logic operation based on the output of the first logic circuit and outputs a result of the combinational logic operation as a converted signal. The converted signal has the same waveform and frequency as those of the clock signal, and the phases of the clock signal and the converted signal are the same or only slightly different.

Abstract: A PLL apparatus and system for generating distributed clocks are disclosed. A synchronizing-edge detector is provided to the PLL apparatus in the PLL system to detect synchronizing edges of the input and output clock signals having gear relationship for the PLL apparatus. The synchronizing-edge detector detects a sample signal the frequency of which is the common divisor of the frequencies of the input and output signal. The PLL apparatus may be provided with a detection terminal connected with one of the input terminals of a pre-divider and loop divider for outputting the sample signal. Alternatively, the PLL system can comprise at least one additional divider coupled to the input and/or output signals of a PLL apparatus to generate the sample signal.

Abstract: An interface module and method is disclosed for receiving the digital image data output of an analog/digital converter and transmitting the digital image data output to the JPEG compression device when the image data is determined to be compressed. The interface module comprises a read control device, an output control device and a memory device. The read control device reads a predetermined number of image lines from the data output of the analog/digital converter and stores these image data in a memory device. The memory device can save the same number of image lines as the memory device built in the JPEG compression device. After reading the predetermined number of image lines, the read control device will generate a control signal to the output control device for sequentially reading an image block from the memory device and sending each of the image block to the JPEG compression device.