Patents by Inventor Chia-Ying YANG
Chia-Ying YANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240363530Abstract: An integrated circuit includes a front-side horizontal conducting line and a front-side vertical conducting line at the front side of the substrate, a transistor in a semiconductor structure at the front side of the substrate, and a backside conducting line at a backside of the substrate. The front-side horizontal conducting line is directly connected to a first terminal of the transistor through a front-side terminal via-connector and directly connected to the front-side horizontal conducting line through a front-side metal-to-metal via-connector. A word connection line directly is connected to a gate terminal of the transistor through a gate via-connector. The backside conducting line is directly connected to a second terminal of the transistor through a backside terminal via-connector. In the integrated circuit, a front-side fuse element is conductively connected to either the front-side vertical conducting line or the front-side horizontal conducting line.Type: ApplicationFiled: July 12, 2024Publication date: October 31, 2024Inventors: Chien-Ying CHEN, Yen-Jen CHEN, Yao-Jen YANG, Meng-Sheng CHANG, Chia-En HUANG
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Publication number: 20240332085Abstract: A method of forming a semiconductor device includes: forming a metal gate structure over a fin that protrudes above a substrate, the metal gate structure being surrounded by an interlayer dielectric (ILD) layer; recessing the metal gate structure below an upper surface of the ILD layer distal from the substrate; after the recessing, forming a first dielectric layer over the recessed metal gate structure; forming an etch stop layer (ESL) over the first dielectric layer and the ILD layer; forming a second dielectric layer over the ESL; performing a first dry etch process to form an opening that extends through the second dielectric layer, through the ESL, and into the first dielectric layer; after the first dry etch process, performing a wet etch process to clean the opening; and after the wet etch process, performing a second dry etch process to extend the opening through the first dielectric layer.Type: ApplicationFiled: June 12, 2024Publication date: October 3, 2024Inventors: Meng Jhe Tsai, Hong-Jie Yang, Meng-Chun Chang, Hao Chiang, Chia-Ying Lee, Huan-Just Lin, Chuan Chang
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Publication number: 20240321500Abstract: A magnetic component includes a core, at least one coil, a first heat dissipating member and a second heat dissipating member. The core includes at least one outer leg and an inner leg. The at least one coil is wound around the inner leg. The first heat dissipating member is disposed on a first side and a top side of the core. The second heat dissipating member is disposed on a second side and the top side of the core. The first heat dissipating member and the second heat dissipating member have a first joint region, a second joint region and a third joint region on the top side. Projections of the first joint region and the second joint region do not overlap with the inner leg. A projection of at least one of the first heat dissipating member and the second heat dissipating member overlaps with the inner leg.Type: ApplicationFiled: March 22, 2024Publication date: September 26, 2024Applicant: CYNTEC CO., LTD.Inventors: Yung-Shou Hsu, Chien-Lin Chen, Shao-Wei Chang, Chun-Ying Liao, Hsieh-Shen Hsieh, Ying-Teng Chang, Chia-Hao Yang
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Publication number: 20240321498Abstract: A magnetic component includes a core and at least one coil. The core includes at least one outer leg and an inner leg. The inner leg is separated from an upper inner surface of the core. The inner leg is at least partially divided into a plurality of separated portions along a length direction of the inner leg. The at least one coil is wound around the inner leg.Type: ApplicationFiled: March 21, 2024Publication date: September 26, 2024Applicant: CYNTEC CO., LTD.Inventors: Yung-Shou Hsu, Chien-Lin Chen, Shao-Wei Chang, Chun-Ying Liao, Hsieh-Shen Hsieh, Ying-Teng Chang, Chia-Hao Yang
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Patent number: 12080641Abstract: An integrated circuit includes a transistor formed in a semiconductor structure, a front-side horizontal conducting line in a first metal layer above the semiconductor structure, and a front-side vertical conducting line in a second metal layer above the first metal layer. The front-side horizontal conducting line is directly connected to a first terminal of the transistor, and the front-side vertical conducting line is directly connected to the front-side horizontal conducting line. In the integrated circuit, a front-side fuse element is conductively connected to the front-side vertical conducting line, and a backside conducting line is directly connected to a second terminal of the transistor. A word connection line extending in the first direction is directly connected to a gate terminal of the transistor.Type: GrantFiled: October 18, 2023Date of Patent: September 3, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-Ying Chen, Yen-Jen Chen, Yao-Jen Yang, Meng-Sheng Chang, Chia-En Huang
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Patent number: 12040233Abstract: A method of forming a semiconductor device includes: forming a metal gate structure over a fin that protrudes above a substrate, the metal gate structure being surrounded by an interlayer dielectric (ILD) layer; recessing the metal gate structure below an upper surface of the ILD layer distal from the substrate; after the recessing, forming a first dielectric layer over the recessed metal gate structure; forming an etch stop layer (ESL) over the first dielectric layer and the ILD layer; forming a second dielectric layer over the ESL; performing a first dry etch process to form an opening that extends through the second dielectric layer, through the ESL, and into the first dielectric layer; after the first dry etch process, performing a wet etch process to clean the opening; and after the wet etch process, performing a second dry etch process to extend the opening through the first dielectric layer.Type: GrantFiled: May 25, 2021Date of Patent: July 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Meng Jhe Tsai, Hong-Jie Yang, Meng-Chun Chang, Hao Chiang, Chia-Ying Lee, Huan-Just Lin, Chuan Chang
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Patent number: 11477630Abstract: A radio system includes a radio voice terminal, a relay server, a command center and a radio network gateway. The radio network gateway includes a communication module in communication with the relay server; a radio voice control module in communication with the first radio voice terminal, receiving a radio voice signal from the first radio voice terminal; and a processing module in communication with the communication module and the radio voice control module, converting the radio voice signal into a digital voice file, executing a voice recognition process to extract at least one keyword from the digital voice file, and transmitting the at least one keyword to the relay server through the communication module.Type: GrantFiled: December 4, 2020Date of Patent: October 18, 2022Assignee: ALPHA NETWORKS INC.Inventors: Shih Chieh Su, Yi Peng Cheng, Chia Ying Yang
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Patent number: 11419866Abstract: The present invention is directed to a depot composition for sustained release delivery of buprenorphine with enhanced stability and bioavailability. The composition is an injectable, low viscosity liquid and can form a depot in situ capable of delivering therapeutic level of buprenorphine over a period of time from one week to 3 months.Type: GrantFiled: January 21, 2019Date of Patent: August 23, 2022Assignee: Foresee Pharmaceuticals Co., Ltd.Inventors: Yuhua Li, MingHsin Li, Chen-Chang Lee, Chia-Ying Yang, Chih-Ying Lin
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Publication number: 20220124473Abstract: A radio system includes a radio voice terminal, a relay server, a command center and a radio network gateway. The radio network gateway includes a communication module in communication with the relay server; a radio voice control module in communication with the first radio voice terminal, receiving a radio voice signal from the first radio voice terminal; and a processing module in communication with the communication module and the radio voice control module, converting the radio voice signal into a digital voice file, executing a voice recognition process to extract at least one keyword from the digital voice file, and transmitting the at least one keyword to the relay server through the communication module.Type: ApplicationFiled: December 4, 2020Publication date: April 21, 2022Inventors: SHIH CHIEH SU, YI PENG CHENG, CHIA YING YANG
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Publication number: 20200345724Abstract: The present invention is directed to a depot composition for sustained release delivery of buprenorphine with enhanced stability and bioavailability. The composition is an injectable, low viscosity liquid and can form a depot in situ capable of delivering therapeutic level of buprenorphine over a period of time from one week to 3 months.Type: ApplicationFiled: January 22, 2018Publication date: November 5, 2020Applicant: Foresee Pharmaceuticals Co., Ltd.Inventors: Yuhua LI, MingHsin LI, Chen-Chang LEE, Chia-Ying YANG, Chih-Ying LIN
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Patent number: 9966494Abstract: A method for manufacturing a polycrystalline silicon ingot includes steps of: a) melting a silicon material in a container disposed in a thermal field to form a molten silicon; b) controlling the thermal field to provide heat to the molten silicon from above the container and to solidify a portion of the molten silicon contacting a base part and at least a portion of a wall part proximate to the base part of the container to form a solid silicon crystalline isolation layer; and c) controlling the thermal field to continuously provide heat to the rest of the molten silicon from above the container and to solidify the rest of the molten silicon gradually from a bottom to a top of the rest of the molten silicon to form a polycrystalline silicon ingot.Type: GrantFiled: August 5, 2015Date of Patent: May 8, 2018Assignee: AUO CRYSTAL CORPORATIONInventors: Kuo-Chen Ho, Ya-Lu Tsai, Chien-Chia Tseng, Chia-Ying Yang
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Patent number: 9911893Abstract: A method for manufacturing a polycrystalline silicon ingot includes steps of: a) melting a silicon material in a container disposed in a thermal field to form a molten silicon; b) controlling the thermal field to provide heat to the molten silicon from above the container and to solidify a portion of the molten silicon contacting a base part and at least a portion of a wall part proximate to the base part of the container to form a solid silicon crystalline isolation layer; and c) controlling the thermal field to continuously provide heat to the rest of the molten silicon from above the container and to solidify the rest of the molten silicon gradually from a bottom to a top of the rest of the molten silicon to form a polycrystalline silicon ingot.Type: GrantFiled: August 5, 2015Date of Patent: March 6, 2018Assignee: AUO CRYSTAL CORPORATIONInventors: Kuo-Chen Ho, Ya-Lu Tsai, Chien-Chia Tseng, Chia-Ying Yang
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Publication number: 20160043266Abstract: A method for manufacturing a polycrystalline silicon ingot includes steps of: a) melting a silicon material in a container disposed in a thermal field to form a molten silicon; b) controlling the thermal field to provide heat to the molten silicon from above the container and to solidify a portion of the molten silicon contacting a base part and at least a portion of a wall part proximate to the base part of the container to form a solid silicon crystalline isolation layer; and c) controlling the thermal field to continuously provide heat to the rest of the molten silicon from above the container and to solidify the rest of the molten silicon gradually from a bottom to a top of the rest of the molten silicon to form a polycrystalline silicon ingot.Type: ApplicationFiled: August 5, 2015Publication date: February 11, 2016Inventors: Kuo-Chen Ho, Ya-Lu TSAI, Chien-Chia TSENG, Chia-Ying YANG