Abstract: An apparatus includes a pseudo address decoder, a programmable logic array, a corresponding value calculation module, a storage element, a subtracter, and a multiplexer. The pseudo address decoder determines a block corresponding to an index of the compression encoding table. The programmable logic array calculates related data of the block determined by the pseudo address decoder. The corresponding value calculation module calculates the corresponding value in accordance with the related data of the block. Non-repeating or non-increasing data of the compression encoding table are stored in the storage element. The subtracter outputs a difference between the index and the address offset in order to read the storage element. The multiplexer selectively outputs the output values calculated by the corresponding value calculation module or the data read from the storage element.

Abstract: A processing method of image compensation for digital camera, after the signal of a digital image is sensed by a proper charged coupled device (CCD ), a color filter array displays this digital image in a sequence by array pattern according to the signal strength of basic color components. The color component compensation can be completed in coordination with the signal composition of the color components that are adjacent to a pixel needed to do color component compensation; enabling digital camera can completely and truly display the captured image picture.

Abstract: The invention relates to a method and circuit for synchronizing two signals triggered by clocks of different frequencies, which samples the lower frequency write-enable signal at both positive and negative edges of the higher frequency clock. If the sampling result at the positive or negative edge of the higher frequency clock is “1”, the state is recorded to be a “lock state” and no sampling is taken from the next opposite edge. If the sampling result at the positive or negative edge is “0”, the state is recorded to be a “sampling state” and the next opposite edge will be sampled. Finally, the sampling results taken at the positive and negative edges are joined to output a synchronized write-enable signal.

Abstract: An apparatus includes a pseudo address decoder, a programmable logic array, a corresponding value calculation module, a storage element, a subtracter, and a multiplexer. The pseudo address decoder determines a block corresponding to an index of the compression encoding table. The programmable logic array calculates related data of the block determined by the pseudo address decoder. The corresponding value calculation module calculates the corresponding value in accordance with the related data of the block. Non-repeating or non-increasing data of the compression encoding table are stored in the storage element. The subtracter outputs a difference between the index and the address offset in order to read the storage element. The multiplexer selectively outputs the output values calculated by the corresponding value calculation module or the data read from the storage element.

Abstract: The invention relates to a method and circuit for synchronizing two signals triggered by clocks of different frequencies, which samples the lower frequency write-enable signal at both positive and negative edges of the higher frequency clock. If the sampling result at the positive or negative edge of the higher frequency clock is “1”, the state is recorded to be a “lock state” and no sampling is taken from the next opposite edge. If the sampling result at the positive or negative edge is “0”, the state is recorded to be a “sampling state” and the next opposite edge will be sampled. Finally, the sampling results taken at the positive and negative edges are joined to output a synchronized write-enable signal.

Abstract: A processing method of image compensation for digital camera, after the signal of a digital image is sensed by a proper charged coupled device (CCD ), a color filter array displays this digital image in a sequence by array pattern according to the signal strength of basic color components. The color component compensation can be completed in coordination with the signal composition of the color components that are adjacent to a pixel needed to do color component compensation; enabling digital camera can completely and truly display the captured image picture.

Abstract: A Discreet Cosine Transform (DCT) circuit consisting of a pipe-lined Single Instruction stream, Multiple Data stream (SIMD) processor array, a transpose memory and a control circuit is provided by exploiting the row-column decomposition method, wherein the processor array is capable of computing one dimensional DCT. In an N-point DCT application, the processor array consists of N PEs (processor elements), each of which can compute a N/2-point inner product. Instead of a conventional Multiplexed Analogue Components (MAC) design, the present DCT circuit computes the N/2-point inner product by a word-parallel bit-serial method, which uses N/2 Read Only Memory (ROM) tables, a Wallace tree and one carry propagate adder. This implementation achieves cost-saving and better timing in comparison to a MAC design. Meanwhile, the circuit also has the advantages of simple data routing, regular structure and modular design, and is suitable for Very Large Scale Integration (VLSI) implementation.