Patents by Inventor Chia-Yu Chan
Chia-Yu Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240140765Abstract: An overhead hoist transfer apparatus includes a rail assembly including a straight rail having an empty section, and a curved rail having a curved empty section; an engine including a first LSD having first and second wheels at two sides respectively; and a second LSD having third and fourth wheels at two sides respectively; a moving carriage driven by the engine and suspended from the rail assembly; first and second guide wheels disposed on the first LSD; third and fourth guide wheels disposed on the second LSD; and two guide boards disposed above a joining point of the straight rail and the curved rail. An elevation of the guide boards is equal to that of the guide wheels. The guide board includes a straight edge and a curved edge.Type: ApplicationFiled: September 27, 2023Publication date: May 2, 2024Inventors: Jung-Chieh Chang, Yi-Sheng Chen, Jen-Yung Hsiao, Chia-Fu Hsiao, Wei-Qi Lao, Chen-Chih Chan, Caung-Yu Liu
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Publication number: 20240116707Abstract: A powered industrial truck includes a lateral movement assembly including four sliding members and four pivotal members both on a wheeled carriage, four links having a first end pivotably secured to the sliding member and a second end pivotably secured to either end of the pivotal member, a motor shaft having two ends pivotably secured to the pivotal members respectively, a first electric motor on one frame member, and four mounts attached to the sliding members respectively; two lift assemblies including a second electric motor, a shaft having two ends rotatably secured to the sliding members respectively, two gear trains at the ends of the shaft respectively, a first gear connected to the second electric motor, a second gear on the shaft, and a first roller chain on the first and second gears; two electric attachments on the platform and being laterally moveable, each attachment. The mount has rollers.Type: ApplicationFiled: September 21, 2023Publication date: April 11, 2024Inventors: Jung-Chieh Chang, Yi-Sheng Chen, Jen-Yung Hsiao, Chia-Fu Hsiao, Wei-Qi Lao, Chen-Chih Chan, Chung-Yu Liu
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Patent number: 11373692Abstract: A delay tracking method and a memory system are provided. The delay tracking method is applied to a memory system supporting a low-frequency-mode (LFM) and a high-frequency-mode (HFM) of an operating clock. The delay tracking method includes the steps of selecting a LFM oscillator for obtaining a LFM delay value when the operating clock is in the HFM; and selecting a HFM oscillator for obtaining a HFM delay value when the operating clock is in the LFM.Type: GrantFiled: February 19, 2021Date of Patent: June 28, 2022Assignee: MediaTek Inc.Inventors: Bo-Wei Hsieh, Chia-Yu Chan, Jou-Ling Chen
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Publication number: 20210174851Abstract: A delay tracking method and a memory system are provided. The delay tracking method is applied to a memory system supporting a low-frequency-mode (LFM) and a high-frequency-mode (HFM) of an operating clock. The delay tracking method includes the steps of selecting a LFM oscillator for obtaining a LFM delay value when the operating clock is in the HFM; and selecting a HFM oscillator for obtaining a HFM delay value when the operating clock is in the LFM.Type: ApplicationFiled: February 19, 2021Publication date: June 10, 2021Applicant: Media Tek Inc.Inventors: Bo-Wei Hsieh, Chia-Yu Chan, Jou-Ling Chen
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Patent number: 10964363Abstract: A delay tracking method and a memory system are provided. The delay tracking method is applied to a memory system supporting a low-frequency-mode (LFM) and a high-frequency-mode (HFM) of an operating clock. The delay tracking method includes the steps of selecting a LFM oscillator for obtaining a LFM delay value when the operating clock is in the HFM; and selecting a HFM oscillator for obtaining a HFM delay value when the operating clock is in the LFM.Type: GrantFiled: August 14, 2019Date of Patent: March 30, 2021Assignee: MediaTek Inc.Inventors: Bo-Wei Hsieh, Chia-Yu Chan, Jou-Ling Chen
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Patent number: 10846018Abstract: A memory system includes a memory controller, a first memory device and a second memory device. The memory controller issues a first clock signal and a second clock signal. The memory controller transmits or receives a data signal. The first memory device receives the first clock signal and the second clock signal. The second memory device receives the first dock signal and the second clock signal. If a first mode register of the first memory device is in a first single-ended mode and a second mode register of the second memory device is in a second single-ended mode, the first memory device transmits or receives the data signal according to the first dock signal, and the second memory device transmits or receives the data signal according to the second clock signal.Type: GrantFiled: March 26, 2018Date of Patent: November 24, 2020Assignee: MEDIATEK INC.Inventors: Bo-Wei Hsieh, Chia-Yu Chan, Shang-Pin Chen
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Patent number: 10810078Abstract: A method of parity training for a dynamic random access memory, DRAM, is disclosed. The method comprises enabling a link error checking and correcting, ECC, functionality in a write operation of the DRAM, and remapping a parity function of a write parity pin to an data inversion function, a data replacing function, or a logical function, whereby data transferred to the DRAM through the write parity pin is used for indicating an inversion operation, a logical operation, or a substitution operation for data of a data pin.Type: GrantFiled: July 2, 2019Date of Patent: October 20, 2020Assignee: MEDIATEK INC.Inventors: Bo-Wei Hsieh, Chia-Yu Chan, Ching-Yeh Hsuan, Jou-Ling Chen
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Publication number: 20200058335Abstract: A delay tracking method and a memory system are provided. The delay tracking method is applied to a memory system supporting a low-frequency-mode (LFM) and a high-frequency-mode (HFM) of an operating clock. The delay tracking method includes the steps of selecting a LFM oscillator for obtaining a LFM delay value when the operating clock is in the HFM; and selecting a HFM oscillator for obtaining a HFM delay value when the operating clock is in the LFM.Type: ApplicationFiled: August 14, 2019Publication date: February 20, 2020Inventors: Bo-Wei HSIEH, Chia-Yu CHAN, Jou-Ling CHEN
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Publication number: 20200012558Abstract: A method of parity training for a dynamic random access memory, DRAM, is disclosed. The method comprises enabling a link error checking and correcting, ECC, functionality in a write operation of the DRAM, and remapping a parity function of a write parity pin to an data inversion function, a data replacing function, or a logical function, whereby data transferred to the DRAM through the write parity pin is used for indicating an inversion operation, a logical operation, or a substitution operation for data of a data pin.Type: ApplicationFiled: July 2, 2019Publication date: January 9, 2020Inventors: Bo-Wei Hsieh, Chia-Yu Chan, Ching-Yeh Hsuan, Jou-Ling Chen
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Patent number: 10141044Abstract: A memory interface circuit includes a plurality of receivers and a signal detector. The plurality of receivers are arranged for receiving at least a clock signal and a plurality of command signals from a memory controller, respectively. The signal detector is arranged for detecting whether the memory interface circuit receives the clock signal or not to generate a detection result to enable or disable the plurality of receivers.Type: GrantFiled: August 25, 2016Date of Patent: November 27, 2018Assignee: MEDIATEK INC.Inventors: Shang-Pin Chen, Chia-Yu Chan, Bo-Wei Hsieh
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Publication number: 20180293026Abstract: A memory system includes a memory controller, a first memory device and a second memory device. The memory controller issues a first clock signal and a second clock signal. The memory controller transmits or receives a data signal. The first memory device receives the first clock signal and the second clock signal. The second memory device receives the first dock signal and the second clock signal. If a first mode register of the first memory device is in a first single-ended mode and a second mode register of the second memory device is in a second single-ended mode, the first memory device transmits or receives the data signal according to the first dock signal, and the second memory device transmits or receives the data signal according to the second clock signal.Type: ApplicationFiled: March 26, 2018Publication date: October 11, 2018Inventors: Bo-Wei HSIEH, Chia-Yu CHAN, Shang-Pin CHEN
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Patent number: 9871518Abstract: A memory interface circuit includes a first variable impedance circuit coupled between a first supply voltage and a pad, and a second variable impedance circuit coupled between a second supply voltage and the pad; wherein when the first supply voltage changes, at least one of the first variable impedance circuit and the second variable impedance circuit is controlled to have different setting in response to the changing of the first supply voltage.Type: GrantFiled: August 25, 2016Date of Patent: January 16, 2018Assignee: MEDIATEK INC.Inventors: Shang-Pin Chen, Chia-Yu Chan, Bo-Wei Hsieh
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Publication number: 20170222647Abstract: A memory interface circuit includes a first variable impedance circuit coupled between a first supply voltage and a pad, and a second variable impedance circuit coupled between a second supply voltage and the pad; wherein when the first supply voltage changes, at least one of the first variable impedance circuit and the second variable impedance circuit is controlled to have different setting in response to the changing of the first supply voltage.Type: ApplicationFiled: August 25, 2016Publication date: August 3, 2017Inventors: Shang-Pin Chen, Chia-Yu Chan, Bo-Wei Hsieh
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Publication number: 20170221544Abstract: A memory interface circuit includes a plurality of receivers and a signal detector. The plurality of receivers are arranged for receiving at least a clock signal and a plurality of command signals from a memory controller, respectively. The signal detector is arranged for detecting whether the memory interface circuit receives the clock signal or not to generate a detection result to enable or disable the plurality of receivers.Type: ApplicationFiled: August 25, 2016Publication date: August 3, 2017Inventors: Shang-Pin Chen, Chia-Yu Chan, Bo-Wei Hsieh
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Patent number: 7836241Abstract: An electronic apparatus having switching unit is described. The electronic apparatus includes a first peripheral device, a second peripheral device and a switching unit. The first peripheral device communicates with the host unit. The second peripheral device communicates with the host unit and the first peripheral device, respectively. The switching unit switches to the host unit and the first peripheral device for allowing the host unit to access the first peripheral device via a first path. The switching unit switches to the host unit and the second peripheral device for allowing the host unit to access the second peripheral device via a second path. The switching unit switches to the first peripheral device and the second peripheral device for allowing the first peripheral device to access the second peripheral device via a third path.Type: GrantFiled: November 14, 2008Date of Patent: November 16, 2010Assignee: Genesys Logic, Inc.Inventors: Nei-chiung Perng, Chih-jung Lin, Ching-jung Yu, Chia-yu Chan
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Publication number: 20100125686Abstract: An electronic apparatus having switching unit is described. The electronic apparatus includes a first peripheral device, a second peripheral device and a switching unit. The first peripheral device communicates with the host unit. The second peripheral device communicates with the host unit and the first peripheral device, respectively. The switching unit switches to the host unit and the first peripheral device for allowing the host unit to access the first peripheral device via a first path. The switching unit switches to the host unit and the second peripheral device for allowing the host unit to access the second peripheral device via a second path. The switching unit switches to the first peripheral device and the second peripheral device for allowing the first peripheral device to access the second peripheral device via a third path.Type: ApplicationFiled: November 14, 2008Publication date: May 20, 2010Applicant: GENESYS LOGIC, INC.Inventors: Nei-chiung Perng, Chih-jung Lin, Ching-jung Yu, Chia-yu Chan
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Patent number: 7446630Abstract: A full range phase shifter circuit includes a power divider, a hybrid coupler, a differential phase shifter, a power combiner and switched attenuators. The power divider, hybrid coupler, differential phase shifter and power combiner comprise lumped elements and can be integrated in semiconductor processes, decreasing the circuit size of the full range phase shifter.Type: GrantFiled: May 17, 2007Date of Patent: November 4, 2008Assignee: National Taiwan UniversityInventors: Chia-Yu Chan, Jean-Fu Kiang
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Publication number: 20080180190Abstract: A full range phase shifter circuit includes a power divider, a hybrid coupler, a differential phase shifter, a power combiner and switched attenuators. The power divider, hybrid coupler, differential phase shifter and power combiner comprise lumped elements and can be integrated in semiconductor processes, decreasing the circuit size of the full range phase shifter.Type: ApplicationFiled: May 17, 2007Publication date: July 31, 2008Inventors: Chia-Yu Chan, Jean-Fu Kiang