Patents by Inventor Chia Yu CHOU

Chia Yu CHOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240143750
    Abstract: A case tampering detection device, used for a computer system covered with a computer case, includes at least one detector for detecting whether the computer case is opened and generating a detection result; a storage unit; a microcontroller unit, coupled to the storage unit, for generating a case tampering event and storing the case tampering event in the microcontroller unit or the storage unit when being powered; and a power supply unit, coupled to the at least one detector, for receiving the detection result, and supplying power to the microcontroller unit when the detection result indicates that the computer case is opened.
    Type: Application
    Filed: December 8, 2022
    Publication date: May 2, 2024
    Applicant: Moxa Inc.
    Inventors: Yoong Tak TAN, Chia-Te CHOU, Jian-Yu LIAO, Tsung-Yi LIN
  • Patent number: 11966255
    Abstract: A fixing structure used to connect a display panel to a housing of an electronic device during manufacture of the electronic device includes a fixing member, an auxiliary member spaced apart from the fixing member, and supporting posts disposed between the fixing member and the auxiliary member. The fixing member is to be bonded to the display panel. A projection of an outer edge of the auxiliary member on a plane of the fixing member is outside of an outer edge of the fixing member. The supporting posts and the auxiliary member are removed after the display panel is bonded to the fixing member. A method for assembling the display panel with the fixing structure is also disclosed.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: April 23, 2024
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Chia-Ju Lin, Fu-Hsin Sung, Meng-Yu Chou
  • Publication number: 20240071537
    Abstract: A multi-fuse memory cell is disclosed. The circuit includes: a first fuse element electrically coupled to a first transistor, a gate of the first transistor is electrically coupled to a first selection signal; a second fuse element electrically coupled to a second transistor, a gate of the second transistor is electrically coupled to a second selection signal, both the first transistor and the second transistor are grounded; and a programming transistor electrically coupled to the first fuse element and the second fuse element, wherein a gate of the programming transistor is electrically coupled to a programming signal.
    Type: Application
    Filed: November 7, 2023
    Publication date: February 29, 2024
    Inventors: Meng-Sheng Chang, Chia-En Huang, Shao-Yu Chou, Yih Wang
  • Patent number: 10090571
    Abstract: A transmission switch includes a dielectric substrate; a conductive ground layer disposed over an upper surface of the dielectric substrate, wherein the conductive ground layer comprises a first ground section and a second ground section separated from the first ground section; a tunable dielectric layer disposed over the conductive ground layer, wherein the tunable dielectric layer has a first dielectric constant at a first DC voltage and a second dielectric constant at a second DC voltage; and a conductive signal layer disposed over the tunable dielectric layer, wherein the conductive signal layer comprises a first signal section, a second signal section, and an impedance-matching section connecting the first signal section and the second signal section.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: October 2, 2018
    Assignee: MICROELECTRONICS TECHNOLOGY, INC.
    Inventors: Chang-Chun Chen, Chia-Yu Chou
  • Patent number: 10044087
    Abstract: A switchable radiator includes a dielectric substrate, a first conductive layer having a slot disposed over an upper surface of the dielectric substrate, a tunable dielectric layer disposed over the first conductive layer, and a second conductive layer disposed over the tunable dielectric layer. The tunable dielectric layer has a first dielectric constant at a first DC voltage and a second dielectric constant at a second DC voltage. The second conductive layer includes a first signal section, a second signal section, and an impedance-matching section connecting the first signal section and the second signal section. The operation method of the switchable radiator includes applying a first DC voltage to the tunable dielectric layer to enable the switchable radiator to radiate energy through the slot and applying a second DC voltage to the tunable dielectric layer to disable the switchable radiator from radiating energy through the slot.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: August 7, 2018
    Assignee: Microelectronics Technology, Inc.
    Inventors: Wei Huang Chen, Chang-Chun Chen, Chia-Yu Chou
  • Publication number: 20180115032
    Abstract: A transmission switch includes a dielectric substrate; a conductive ground layer disposed over an upper surface of the dielectric substrate, wherein the conductive ground layer comprises a first ground section and a second ground section separated from the first ground section; a tunable dielectric layer disposed over the conductive ground layer, wherein the tunable dielectric layer has a first dielectric constant at a first DC voltage and a second dielectric constant at a second DC voltage; and a conductive signal layer disposed over the tunable dielectric layer, wherein the conductive signal layer comprises a first signal section, a second signal section, and an impedance-matching section connecting the first signal section and the second signal section.
    Type: Application
    Filed: October 24, 2016
    Publication date: April 26, 2018
    Inventors: CHANG-CHUN CHEN, CHIA-YU CHOU
  • Publication number: 20180108970
    Abstract: A switchable radiator includes a dielectric substrate, a first conductive layer having a slot disposed over an upper surface of the dielectric substrate, a tunable dielectric layer disposed over the first conductive layer, and a second conductive layer disposed over the tunable dielectric layer. The tunable dielectric layer has a first dielectric constant at a first DC voltage and a second dielectric constant at a second DC voltage. The second conductive layer includes a first signal section, a second signal section, and an impedance-matching section connecting the first signal section and the second signal section. The operation method of the switchable radiator includes applying a first DC voltage to the tunable dielectric layer to enable the switchable radiator to radiate energy through the slot and applying a second DC voltage to the tunable dielectric layer to disable the switchable radiator from radiating energy through the slot.
    Type: Application
    Filed: October 14, 2016
    Publication date: April 19, 2018
    Inventors: WEI HUANG CHEN, CHANG-CHUN CHEN, CHIA-YU CHOU
  • Patent number: 9105956
    Abstract: A laminated waveguide diplexer includes an upper conductive layer having a first slot and a second slot; a first line crossing over the first slot; a first shielding conductor disposed over the first line; a plurality of first conductive pillars connecting the upper conductive layer and the first shielding conductor; a second line crossing over the second slot; a second shielding conductor disposed over the second line; and a plurality of second conductive pillars connecting the upper conductive layer and the second shielding conductor.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: August 11, 2015
    Assignee: Microelectronics Technology, Inc.
    Inventors: Ting Yi Huang, Chia Yu Chou
  • Patent number: 9059498
    Abstract: A laminated waveguide diplexer includes a first laminated waveguide, a second laminated waveguide, and a coupling metal connecting the first and second laminated waveguides. The first laminated waveguide has a first upper conductor with a first slot, and the second laminated waveguide has a second upper conductor with a second slot. The coupling metal includes a first line crossing over the first slot and a second line crossing over the second slot. In addition, the laminated waveguide diplexer further includes a first via connecting the first upper conductor and the first line, and a second via connecting the second upper conductor and the second line. The first and second vias are adjacent to the first and second slots, respectively, such that the first and second lines are short stubs for respective radio frequency signals propagating thereon.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: June 16, 2015
    Assignee: Microelectronics Technology, Inc.
    Inventors: Ting Yi Huang, Chia Yu Chou
  • Publication number: 20140240058
    Abstract: A laminated waveguide diplexer includes a first laminated waveguide, a second laminated waveguide, and a coupling metal connecting the first and second laminated waveguides. The first laminated waveguide has a first upper conductor with a first slot, and the second laminated waveguide has a second upper conductor with a second slot. The coupling metal includes a first line crossing over the first slot and a second line crossing over the second slot. In addition, the laminated waveguide diplexer further includes a first via connecting the first upper conductor and the first line, and a second via connecting the second upper conductor and the second line. The first and second vias are adjacent to the first and second slots, respectively, such that the first and second lines are short stubs for respective radio frequency signals propagating thereon.
    Type: Application
    Filed: October 4, 2013
    Publication date: August 28, 2014
    Applicant: MICROELECTRONICS TECHNOLOGY, INC.
    Inventors: Ting Yi HUANG, Chia Yu CHOU
  • Publication number: 20140184355
    Abstract: A laminated waveguide diplexer includes an upper conductive layer having a first slot and a second slot; a first line crossing over the first slot; a first shielding conductor disposed over the first line; a plurality of first conductive pillars connecting the upper conductive layer and the first shielding conductor; a second line crossing over the second slot; a second shielding conductor disposed over the second line; and a plurality of second conductive pillars connecting the upper conductive layer and the second shielding conductor.
    Type: Application
    Filed: November 15, 2013
    Publication date: July 3, 2014
    Applicant: MICROELECTRONICS TECHNOLOGY, INC.
    Inventors: Ting Yi HUANG, Chia Yu CHOU