Patents by Inventor Chia-Yu Huang

Chia-Yu Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11978669
    Abstract: The present disclosure provides a semiconductor structure. The structure includes a semiconductor substrate, a gate stack over a first portion of a top surface of the semiconductor substrate; and a laminated dielectric layer over at least a portion of a top surface of the gate stack. The laminated dielectric layer includes at least a first sublayer and a second sublayer. The first sublayer is formed of a material having a dielectric constant lower than a dielectric constant of a material used to form the second sublayer and the material used to form the second sublayer has an etch selectivity higher than an etch selectivity of the material used to form the first sublayer.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: May 7, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Lin Chuang, Chia-Hao Chang, Sheng-Tsung Wang, Lin-Yu Huang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11955154
    Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Tung Huang, Jen-Yu Wang, Po-Chun Yang, Yi-Ting Wu, Yung-Ching Hsieh, Jian-Jhong Chen, Chia-Wei Lee
  • Patent number: 11955535
    Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to one embodiment includes an active region including a channel region and a source/drain region adjacent the channel region, a gate structure over the channel region of the active region, a source/drain contact over the source/drain region, a dielectric feature over the gate structure and including a lower portion adjacent the gate structure and an upper portion away from the gate structure, and an air gap disposed between the gate structure and the source/drain contact. A first width of the upper portion of the dielectric feature along a first direction is greater than a second width of the lower portion of the dielectric feature along the first direction. The air gap is disposed below the upper portion of the dielectric feature.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Hao Chang, Lin-Yu Huang, Sheng-Tsung Wang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11949990
    Abstract: This document describes apparatuses and techniques enabling a scale down capture preview for a panorama capture user interface. This scale down preview enables users to more-easily and more-accurately capture images for a panorama.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: April 2, 2024
    Assignee: Google LLC
    Inventors: Lawrence Chia-Yu Huang, Carsten Hinz, Chorong Hwang Johnston, Mike Ma, Isaac William Reynolds
  • Patent number: 11948879
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a first dielectric material disposed over the device, and an opening is formed in the first dielectric material. The semiconductor device structure further includes a conductive structure disposed in the opening, and the conductive structure includes a first sidewall. The semiconductor device structure further includes a surrounding structure disposed in the opening, and the surrounding structure surrounds the first sidewall of the conductive structure. The surrounding structure includes a first spacer layer and a second spacer layer adjacent the first spacer layer. The first spacer layer is separated from the second spacer layer by an air gap.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11942464
    Abstract: In an embodiment, a method includes: aligning a first package component with a second package component, the first package component having a first region and a second region, the first region including a first conductive connector, the second region including a second conductive connector; performing a first laser shot on a first portion of a top surface of the first package component, the first laser shot reflowing the first conductive connector of the first region, the first portion of the top surface of the first package component completely overlapping the first region; and after performing the first laser shot, performing a second laser shot on a second portion of the top surface of the first package component, the second laser shot reflowing the second conductive connector of the second region, the second portion of the top surface of the first package component completely overlapping the second region.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Jan Pei, Hsiu-Jen Lin, Wei-Yu Chen, Philip Yu-Shuan Chung, Chia-Shen Cheng, Kuei-Wei Huang, Ching-Hua Hsieh, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20240099030
    Abstract: A bonded assembly includes an interposer; a semiconductor die that is attached to the interposer and including a planar horizontal bottom surface and a contoured sidewall; a high bandwidth memory (HBM) die that is attached to the interposer; and a dielectric material portion contacting the semiconductor die and the interposer. The contoured sidewall includes a vertical sidewall segment and a non-horizontal, non-vertical surface segment that is adjoined to a bottom edge of the vertical sidewall segment and is adjoined to an edge of the planar horizontal bottom surface of the semiconductor die. The vertical sidewall segment and the non-horizontal, non-vertical surface segment are in contact with the dielectric material portion. The contoured sidewall may provide a variable lateral spacing from the HBM die to reduce local stress in a portion of the HBM die that is proximal to the interposer.
    Type: Application
    Filed: April 20, 2023
    Publication date: March 21, 2024
    Inventors: Kuan-Yu Huang, Sung-Hui Huang, Kuo-Chiang Ting, Chia-Hao Hsu, Hsien-Pin Hsu, Chih-Ta Shen, Shang-Yun Hou
  • Patent number: 11934027
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 19, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Publication number: 20240088195
    Abstract: An image sensor device includes a semiconductor substrate, a radiation sensing member, a shallow trench isolation, and a color filter layer. The radiation sensing member is in the semiconductor substrate. An interface between the radiation sensing member and the semiconductor substrate includes a direct band gap material. The shallow trench isolation is in the semiconductor substrate and surrounds the radiation sensing member. The color filter layer covers the radiation sensing member.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yu WEI, Yen-Liang LIN, Kuo-Cheng LEE, Hsun-Ying HUANG, Hsin-Chi CHEN
  • Publication number: 20240071537
    Abstract: A multi-fuse memory cell is disclosed. The circuit includes: a first fuse element electrically coupled to a first transistor, a gate of the first transistor is electrically coupled to a first selection signal; a second fuse element electrically coupled to a second transistor, a gate of the second transistor is electrically coupled to a second selection signal, both the first transistor and the second transistor are grounded; and a programming transistor electrically coupled to the first fuse element and the second fuse element, wherein a gate of the programming transistor is electrically coupled to a programming signal.
    Type: Application
    Filed: November 7, 2023
    Publication date: February 29, 2024
    Inventors: Meng-Sheng Chang, Chia-En Huang, Shao-Yu Chou, Yih Wang
  • Publication number: 20240069923
    Abstract: A system includes one or more data processors configured to run a basic input/output system (BIOS) service and a bootloader configuration manager for tuning kernel parameters. The system further includes a non-transitory computer-readable storage medium containing instructions which, when executed on the one or more data processors, cause the one or more data processors to perform operations. The operations include receiving administrative inputs and checking the administrative inputs against a checklist to determine whether any errors are introduced by the administrative inputs. The operations further include writing the administrative inputs to a temporal configuration file in response to no errors being introduced by the administrative inputs. The operations further include exporting the temporal configuration file to a designated output path. The exported temporal configuration file includes kernel parameter settings for configuring a bootloader of a computing device.
    Type: Application
    Filed: August 24, 2022
    Publication date: February 29, 2024
    Inventors: Hsuan-Ho CHUANG, Tong-Pai HUANG, Jia-Yu JUANG, Chia-Jui LEE
  • Patent number: 11583538
    Abstract: The present invention provides compounds of Formula I: wherein X, R1, R2, R3 and R4 are as defined herein, or a stereoisomer, tautomer, pharmaceutically acceptable salt, prodrug ester or solvate form thereof, wherein all of the variables are as defined herein. These compounds are effective at modulating the TREX1 protein and thus can be used as medicaments for treating or preventing disorders affected by the inhibition of TREX1.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: February 21, 2023
    Assignee: VENENUM BIODESIGN, LLC
    Inventors: Jeffrey J. Letourneau, Kiruthika Selvarangan Elamparuthi, Chia-Yu Huang, Venugopalareddy Bommireddy Venkata
  • Publication number: 20220213111
    Abstract: The present invention provides compounds of Formula I: wherein {circle around (A)}, X, R1, R2, R3 and R4 are as defined herein, or a stereoisomer, tautomer, pharmaceutically acceptable salt, prodrug ester or solvate form thereof, wherein all of the variables are as defined herein. These compounds are effective at modulating the TREX1 protein and thus can be used as medicaments for treating or preventing disorders affected by the inhibition of TREX1.
    Type: Application
    Filed: March 8, 2022
    Publication date: July 7, 2022
    Applicant: VENENUM BIODESIGN, LLC
    Inventors: Jeffrey J. LETOURNEAU, Kiruthika SELVARANGAN ELAMPARUTHI, Chia-Yu HUANG, Venugopalareddy BOMMIREDDY VENKATA
  • Publication number: 20220132031
    Abstract: This document describes apparatuses and techniques enabling a scale down capture preview for a panorama capture user interface. This scale down preview enables users to more-easily and more-accurately capture images for a panorama.
    Type: Application
    Filed: September 26, 2019
    Publication date: April 28, 2022
    Applicant: Google LLC
    Inventors: Lawrence Chia-Yu Huang, Carsten Hinz, Chorong Hwang Johnston, Mike Ma, Isaac William Reynolds
  • Patent number: 11306098
    Abstract: The present invention provides compounds of Formula I wherein X, R1, R2, R3 and R4 are as defined herein, or a stereoisomer, tautomer, pharmaceutically acceptable salt, prodrug ester or solvate form thereof, wherein all of the variables are as defined herein. These compounds are effective at modulating the TREX1 protein and thus can be used as medicaments for treating or preventing disorders affected by the inhibition of TREX1.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: April 19, 2022
    Assignee: Venenum Biodesign, LLC
    Inventors: Jeffrey J. Letourneau, Kiruthika Selvarangan Elamparuthi, Chia-Yu Huang, Venugopalareddy Bommireddy Venkata
  • Publication number: 20220048936
    Abstract: The present invention provides compounds of Formula I?: wherein W, X, Y, Z, Z1, Z2, R1, R2, R3, R4 and R5 are as defined herein, or a stereoisomer, tautomer, pharmaceutically acceptable salt, prodrug ester or solvate form thereof, wherein all of the variables are as defined herein. These compounds are effective at modulating the STING protein and thus can be used as medicaments for treating or preventing disorders affected by the agonism of STING.
    Type: Application
    Filed: September 7, 2021
    Publication date: February 17, 2022
    Applicant: Venenum Biodesign, LLC
    Inventors: David J. DILLER, Axel METZGER, David E. KAELIN, JR., Steven PAGET, Chia-Yu HUANG, Brian F. MCGUINNESS, Audrey Julie HOSPITAL, William Ronald SOLVIBILE, JR.
  • Patent number: 11236055
    Abstract: The present invention relates to sulfonamide compounds of formula (I) and formula (II), or a pharmaceutically acceptable salt thereof. The present sulfonamide compounds are useful non-systemic TGR5 agonists that can be used to treat diabetic diseases in human. The present invention provides a pharmaceutical composition containing sulfonamide compounds of formula (I) and formula (II) and a method of making as well as a method of using same in treating patients inflicted with metabolic disorders by administering same. The compounds of the present invention may be used in combination with additional anti-diabetic drugs.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: February 1, 2022
    Assignee: VENENUM BIODESIGN, LLC
    Inventors: Chia-Yu Huang, Brian F. McGuinness, Dongchuan Shi, Steven G. Kultgen, Jeffrey J. Letourneau, James R. Beasley, Philip D. Stein, Andrew G. Cole
  • Patent number: 11161864
    Abstract: The present invention provides compounds of Formula I?: wherein , W, X, Y, Z, Z1, Z2, R1, R2, R3, R4 and R5 are as defined herein, or a stereoisomer, tautomer, pharmaceutically acceptable salt, prodrug ester or solvate form thereof, wherein all of the variables are as defined herein. These compounds are effective at modulating the STING protein and thus can be used as medicaments for treating or preventing disorders affected by the agonism of STING.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: November 2, 2021
    Assignee: VENENUM BIODESIGN, LLC
    Inventors: David J. Diller, Axel Metzger, David E. Kaelin, Jr., Steven Paget, Chia-Yu Huang, Brian F. Mcguinness, Audrey Julie Hospital, William Ronald Solvibile, Jr.
  • Publication number: 20210060041
    Abstract: Methods for treating bladder cancer and solid tumors are disclosed. The methods include administering to a patient a compound of formula 1 Pharmaceutical compositions of compound 1 are also disclosed.
    Type: Application
    Filed: November 12, 2020
    Publication date: March 4, 2021
    Applicant: Venenum Biodesign, LLC
    Inventors: Brian F. McGUINNESS, Chia-Yu HUANG
  • Publication number: 20210015829
    Abstract: The present invention provides compounds of Formula I: wherein X, R1, R2, R3 and R4 are as defined herein, or a stereoisomer, tautomer, pharmaceutically acceptable salt, prodrug ester or solvate form thereof, wherein all of the variables are as defined herein. These compounds are effective at modulating the TREX1 protein and thus can be used as medicaments for treating or preventing disorders affected by the inhibition of TREX1.
    Type: Application
    Filed: October 6, 2020
    Publication date: January 21, 2021
    Applicant: Venenum Biodesign, LLC
    Inventors: Jeffrey J. LETOURNEAU, Kiruthika SELVARANGAN ELAMPARUTHI, Chia-Yu HUANG, Venugopalareddy BOMMIREDDY VENKATA