Abstract: An LGA (Land Grid Array) semiconductor package mainly comprises a substrate, a chip, a soldering layer and a foot stand. The chip is disposed on a top surface of the substrate and is electrically connected to a plurality of metal pads formed on a bottom surface of the substrate. The soldering layer is disposed on the metal pads with a first thickness slightly protruded from the bottom surface of the substrate. Additionally, the foot stand is disposed under the substrate with a second thickness protruded from the bottom surface of the substrate, wherein the second thickness is greater than the first thickness. Therefore, the soldering layer of the LGA semiconductor package is free from scratches and damages during shipping and handling processes. Moreover, the LGA semiconductor package can be surface-mounted to a printed circuit board with pre-applied solder or pre-mounted solder balls to increase the implementations of LGA semiconductor packages.

Abstract: A multi-chip IC package encapsulates a chip under asymmetric longer single-side leads. The package mainly comprises a plurality of leads that have asymmetric length at two sides of a leadframe, a plurality of die-attach tape strips, a first chip having a plurality of single-side pads under the longer side leads, at least a second chip disposed above the longer side leads, a plurality of bonding wires and a molding compound. The die-attach tape strips are mutually parallel and adhered onto the lower surfaces of the longer side leads to adhere the first chip. There is at least a mold-flow channel formed through the first chip, the longer side leads and the die-attach tape strips. The bonding wires electrically connect the single-side pads of the first chip to the leads at the two sides of the leadframe through a non-central gap. The molding compound encapsulates the first chip, the second chip, the bonding wires and portions of the leads at the two sides of the leadframe and fills up the mold-flow channel.

Abstract: A multi-chip IC package encapsulates a chip under asymmetric longer single-side leads. The package mainly comprises a plurality of leads that have asymmetric length at two sides of a leadframe, a plurality of die-attach tape strips, a first chip having a plurality of single-side pads under the longer side leads, at least a second chip disposed above the longer side leads, a plurality of bonding wires and a molding compound. The die-attach tape strips are mutually parallel and adhered onto the lower surfaces of the longer side leads to adhere the first chip. There is at least a mold-flow channel formed through the first chip, the longer side leads and the die-attach tape strips. The bonding wires electrically connect the single-side pads of the first chip to the leads at the two sides of the leadframe through a non-central gap. The molding compound encapsulates the first chip, the second chip, the bonding wires and portions of the leads at the two sides of the leadframe and fills up the mold-flow channel.

Abstract: A stacking structure of chip package disclosed herein includes a lead frame having a plurality of supporting fingers and a plurality of leads; a first chip arranged on one side of the lead frame by utilizing a first connecting element so as to partially cover these supporting fingers, wherein the supporting fingers stretch from the edge of the first chip toward the first chip to provide a support; a second chip arranged on the opposite side of the lead frame at the corresponding position of the first chip by utilizing a second connecting element to partially covering the supporting fingers, wherein the first chip, the second chip and the partially-covered supporting fingers are cooperated to define an open mold-flowing trench; an electrical-connecting element to electrically connect the first chip, the second chip and the leads; and a molding compound utilized to cover the first chip, the second chip, the electrical-connecting element and some of the lead frame, wherein the molding compound flows through the

Abstract: A photosensitive semiconductor package and a method for fabricating the same are proposed. The package includes a carrier having a first surface, an opposite second surface, and an opening penetrating the carrier; a photosensitive chip having an active surface and a non-active surface, wherein a plurality of bond pads are formed close to edges of the active surface, and the chip is mounted via corner positions of its active surface to the second surface of the carrier, with the bond pads being exposed via the opening; a plurality of bonding wires formed in the opening, for electrically connecting the bond pads of the chip to the first surface of the carrier; a light-penetrable unit attached to the active surface of the chip and received in the opening; and an encapsulant for encapsulating the bonding wires and peripheral sides of the chip to seal the opening.

Abstract: A photosensitive semiconductor package and a method for fabricating the same are proposed. The package includes a carrier having a first surface, an opposite second surface, and an opening penetrating the carrier; a photosensitive chip having an active surface and a non-active surface, wherein a plurality of bond pads are formed close to edges of the active surface, and the chip is mounted via corner positions of its active surface to the second surface of the carrier, with the bond pads being exposed via the opening; a plurality of bonding wires formed in the opening, for electrically connecting the bond pads of the chip to the first surface of the carrier; a light-penetrable unit attached to the active surface of the chip and received in the opening; and an encapsulant for encapsulating the bonding wires and peripheral sides of the chip to seal the opening.

Abstract: A micro BGA package comprises a die, a wiring board, a plurality of metal bonding wires, a plurality of solder balls, and a package body. The wiring board has a die-attaching surface, a surface-mounting surface with solder balls, and lateral surfaces between the die-attaching surface and the surface-mounting surface. The package body has a fastener covering and extending around the lateral surfaces of the wiring board for improving the bonding strength between wiring board and die and avoiding delamination. Preferably, the wiring board has a plurality of support bars for supporting the wiring board during molding.

Abstract: A micro BGA package comprises a die, a wiring board, a plurality of metal bonding wires, a plurality of solder balls, and a package body. The wiring board has a die-attaching surface, a surface-mounting surface with solder balls, and lateral surfaces between the die-attaching surface and the surface-mounting surface. The package body has a fastener covering and extending around the lateral surfaces of the wiring board for improving the bonding strength between wiring board and die and avoiding delamination. Preferably, the wiring board has a plurality of support bars for supporting the wiring board during molding.

Abstract: A stacked integrated circuit structure, in which main package bodies of a plurality of integrated circuits are stacked on each other. Connections between leads of the stacked integrated circuits are made by means of a stacking substrate. Therein, each of two surfaces of the stacking substrate has a plurality of terminals electrically connected to corresponding terminals. The stacking substrate includes a plurality of through vias as well, which connect to the corresponding terminals of the two surfaces. For two stacked integrated circuits, a hole can be defined in the stacking substrate, which housed the main package body of one of the two stacked integrated circuits, or by means of a plurality of separated substrates arranged around the perimeter of the main package body of one of the two stacked integrated circuits, so that the thickness of the stacked integrated circuits can be reduced.