Abstract: A LED packaging module includes a plurality of LED chips, a wiring layer, and an encapsulant component. The LED chips are spaced apart, each of which includes chip first, chip second, and chip side surfaces, and an electrode unit. The wiring layer is disposed on the chip second surfaces, has first, second, and side wiring layer surfaces, and is divided into a plurality of wiring parts spaced apart. The first wiring layer surface contacts and is electrically connected to the electrode units. The encapsulant component includes first and second encapsulating layers, covers the chip side surfaces, the chip first surfaces, and the side wiring layer surface, and fills gaps among the wiring parts. Each LED chip has a thickness represented by TA, the first encapsulating layer has a thickness represented by TB, and TA and TB satisfy a relationship: TB/TA?1.

Abstract: A method and wafer stack that includes a first wafer component, a second wafer component, and third wafer component. The first wafer component includes a frontside and a backside. The wafer stack also includes a second wafer component having a frontside and a backside, such that the frontside of the second wafer component is bonded to the frontside of the first wafer component. In addition, the wafer stack includes a third wafer component having a frontside and a backside, such that the frontside of the third wafer component is bonded to the backside of the second wafer component. The first wafer component includes a composite metal grid array with one or more photodiodes formed on the backside.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a magnetic tunneling junction (MTJ) and a spin Hall electrode (SHE). The MTJ includes a free layer, a reference layer and a barrier layer lying between the free layer and the reference layer. The SHE is in contact with the MTJ, and configured to convert a charge current to a spin current for programming the MTJ. The SHE is formed of an alloy comprising at least one heavy metal element and at least one light transition metal element. The heavy metal element is selected from metal elements with one or more valence electrons filling in 5d orbitals, and the light transition metal element is selected from transition metal elements with one or more valence electrons partially filling in 3d orbitals.

Abstract: An over-current protection device includes an electrode layer and a heat-sensitive layer. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic, and is laminated between a top metal layer and a bottom metal layer of the electrode layer. The heat-sensitive layer includes a polymer matrix and a conductive filler. The polymer matrix includes a fluorine-containing copolymer, and its melting point ranges from 210° C. to 240° C. The conductive filler consists of carbon black solely, and is used to form an electrically conductive path in the heat-sensitive layer. In addition, the over-current protection device has a resistance-jump ratio ranging from 1.2 to 1.3 between 40° C. and 130° C.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a magnetic tunneling junction (MTJ) and a spin Hall electrode (SHE). The MTJ includes a free layer, a reference layer and a barrier layer lying between the free layer and the reference layer. The SHE is in contact with the MTJ, and configured to convert a charge current to a spin current for programming the MTJ. The SHE is formed of an alloy comprising at least one heavy metal element and at least one light transition metal element. The heavy metal element is selected from metal elements with one or more valence electrons filling in 5 d orbitals, and the light transition metal element is selected from transition metal elements with one or more valence electrons partially filling in 3 d orbitals.

Abstract: An over-current protection device includes an electrode layer and a heat-sensitive layer. The heat-sensitive layer contacts a top metal layer and a bottom metal layer of the electrode layer, and is laminated therebetween. In addition, the heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic and includes a polymer matrix and a conductive filler. The polymer matrix includes a first fluoropolymer, by which the over-current protection device has a starting jump temperature of resistance ranging from 184° C. to 192° C. The conductive filler includes carbon black and a metal compound, thereby forming an electrically conductive path in the heat-sensitive layer.

Abstract: A semiconductor device and method of manufacture are provided. In some embodiments a treatment process is utilized to treat a work function layer. The treatment prevents excessive oxidation of the work function layer during subsequent processing steps, such as application of a subsequent photoresist material, thereby allowing the work function layer to be thinner than otherwise.

Abstract: An interconnect fabrication method is disclosed herein that utilizes a disposable etch stop hard mask over a gate structure during source/drain contact formation and replaces the disposable etch stop hard mask with a dielectric feature (in some embodiments, dielectric layers having a lower dielectric constant than a dielectric constant of dielectric layers of the disposable etch stop hard mask) before gate contact formation. An exemplary device includes a contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion separated by a spacing and a dielectric feature disposed over a gate structure, where the dielectric feature and the gate structure fill the spacing between the first sidewall CESL portion and the second sidewall CESL portion. The dielectric feature includes a bulk dielectric over a dielectric liner. The dielectric liner separates the bulk dielectric from the gate structure and the CESL.

Abstract: A method includes forming a device region over a substrate; forming a first dielectric layer over the device region; forming an opening in the first dielectric layer; conformally depositing a first conductive material along sidewalls and bottom surfaces of the opening; depositing a second conductive material on the first conductive material to fill the opening, wherein the second conductive material is different from the first conductive material; and performing a first thermal process to form an interface region extending from a first region of the first conductive material to a second region of the second conductive material, wherein the interface region includes a homogeneous mixture of the first conductive material and the second conductive material.

Abstract: A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first nanostructure stacked over and spaced apart from a second nanostructure, a gate stack wrapping around the first nanostructure and the second nanostructure, a source/drain feature adjoining the first nanostructure and the second nanostructure, and a first inner spacer layer interposing the gate stack and the source/drain feature and interposing the first nanostructure and the second nanostructure. A dopant in the source/drain feature has a first concentration at an interface between the first inner spacer layer and the source/drain feature and a second concentration at a first distance away from the interface. The first concentration is higher than the second concentration.

Abstract: A method for configuring a plurality of memory units and a plurality of logic units in an integrated circuit includes providing a plurality of predefined parameters of the plurality of memory units, parsing the plurality of predefined parameters to generate a plurality of parsed parameters, compiling the plurality of memory units and the plurality of logic units at the same stage to generate a plurality of candidates of mapping results according to the plurality of parsed parameters, selecting a candidate of the mapping results from the plurality of candidates of the mapping results, and disposing the plurality of memory units and the plurality of logic units onto the integrated circuit according to the candidate of the mapping results.

Abstract: A radio frequency transceiver device includes an antenna unit, a first matching circuit, a receiver circuit, a second matching circuit, a transmitter circuit, and an auxiliary circuit. The receiver circuit includes a mixer unit. The auxiliary circuit includes a first transformer coil and a second transformer coil. The first matching circuit and the receiver circuit are configured to form a first signal reception channel to receive, process, and transmit the first radio frequency signal to the mixer unit when the first radio frequency signal is a high gain radio frequency signal. The second matching circuit and the auxiliary circuit are configured to form a second signal reception channel to receive, process, and transmit the first radio frequency signal to the mixer unit when the first radio frequency signal is a middle-low gain radio frequency signal. Another radio frequency signal transceiver device further includes a third matching circuit.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a polysilicon layer arranged on an upper surface of a base substrate. A dielectric layer is arranged over the polysilicon layer, and an active semiconductor layer is arranged over the dielectric layer. A semiconductor material is arranged vertically on the upper surface of the base substrate and laterally beside the active semiconductor layer.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes an epitaxial layer arranged on a semiconductor body. A trap-rich layer is arranged on the epitaxial layer, a dielectric layer is arranged on the trap-rich layer, and an active semiconductor layer is arranged on the dielectric layer. A semiconductor material is arranged on the epitaxial layer and laterally beside the active semiconductor layer. The epitaxial layer continuously extends from directly below the trap-rich layer to directly below the semiconductor material.

Abstract: A system and method for deploying software packages for end devices that communicate through a mobile network is disclosed. A deployment orchestrator is coupled to the mobile network. End devices communicate with each other through the mobile network. At least one of end devices includes a support package repository storing software packages. When a new end device requires software package deployment, the deployment orchestrator locates at least one of the end devices with the support package repository. The new end device receives software packages from the end device including the support package repository through the mobile network.

Abstract: A heat source detection system includes an infrared light detector, a visible light detector, and a processing unit. The processing unit performs an operation according to at least one instruction, wherein the operation includes steps of: acquiring an infrared light image from the infrared light detector; identifying at least a heat source target according to at least one heat source edge in the infrared light image; determining whether at least one preset condition occurs in the at least one heat source target; and activating the visible light detector when the at least preset condition occurs in the at least one heat source target.

Abstract: A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer.

Abstract: A light-emitting diode (LED) packaging module includes LED chips, a wiring layer, and an encapsulant component. Each of the LED chips includes a chip first surface, a chip second surface, a chip side surface, and an electrode unit. The wiring layer is disposed on the chip second surfaces of the LED chips, and contacts and is electrically connected to the electrode units. The encapsulant component includes a first encapsulating layer that covers the chip side surface, and a second encapsulating layer that covers the wiring layer. The LED chip has a thickness TA, the first encapsulating layer has a thickness TB, in which TB/TA?1.

Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.