Patents by Inventor Chia-Yu Lee
Chia-Yu Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12292695Abstract: An EUV lithographic apparatus includes a wafer stage and a particle removing assembly for cleaning a wafer for an extreme ultraviolet (EUV) lithographic apparatus. The wafer stage includes a measurement side and an exposure side. The particle removing assembly includes particle removing electrodes, an exhaust device and turbomolecular pumps. The particle removing electrodes is configured to direct debris from the chamber by suppressing turbulence such that the debris can be exhausted from the wafer stage to the outside of the processing apparatus. In some embodiments, turbomolecular pumps are turned off in the measurement side of the wafer stage so that an exhaust flow can be guided to an exposure side of the wafer stage. In some embodiments, the speed of voltage rise to the electrodes of the wafer chuck is adjusted.Type: GrantFiled: August 7, 2023Date of Patent: May 6, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tao-Hsin Chen, Li-Jui Chen, Chia-Yu Lee
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Patent number: 12032303Abstract: An EUV lithographic apparatus includes a wafer stage and a particle removing assembly for cleaning a wafer for an extreme ultraviolet (EUV) lithographic apparatus. The wafer stage includes a measurement side and an exposure side. The particle removing assembly includes particle removing electrodes, an exhaust device and turbomolecular pumps. The particle removing electrodes is configured to direct debris from the chamber by suppressing turbulence such that the debris can be exhausted from the wafer stage to the outside of the processing apparatus. In some embodiments, turbomolecular pumps are turned off in the measurement side of the wafer stage so that an exhaust flow can be guided to an exposure side of the wafer stage. In some embodiments, the speed of voltage rise to the electrodes of the wafer chuck is adjusted.Type: GrantFiled: October 18, 2021Date of Patent: July 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tao-Hsin Chen, Li-Jui Chen, Chia-Yu Lee
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Publication number: 20240191388Abstract: An electrolytic polishing treatment method for a nickel-based alloy workpiece made by lamination manufacturing comprises the following steps. Step (A) comprises performing a sandblasting treatment on the nickel-based alloy workpiece, followed by ultrasonic oscillation of the sandblasted nickel-based alloy workpiece in an oxalic acid solution. Step (B) comprises placing the nickel-based alloy workpiece in an electrolyte solution containing methanol, sulfuric acid, and perchloric acid and performing electrolytic polishing on the nickel-based alloy workpiece at a constant voltage after step (A). The processes of oxalic acid activation and electrolytic polishing are used to avoid the problems of residual stress and processing directionality caused by conventional mechanical processing and make the surface properties of the entire workpiece uniform.Type: ApplicationFiled: December 7, 2023Publication date: June 13, 2024Inventors: CHUN-HSIANG KAO, YI-CHERNG FERNG, YING-SUN HUANG, KUO-KUANG JEN, SHUN-YI JIAN, CHIA-YU LEE, JUNG-CHOU HUNG, PO-JEN YANG
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Publication number: 20230375951Abstract: An EUV lithographic apparatus includes a wafer stage and a particle removing assembly for cleaning a wafer for an extreme ultraviolet (EUV) lithographic apparatus. The wafer stage includes a measurement side and an exposure side. The particle removing assembly includes particle removing electrodes, an exhaust device and turbomolecular pumps. The particle removing electrodes is configured to direct debris from the chamber by suppressing turbulence such that the debris can be exhausted from the wafer stage to the outside of the processing apparatus. In some embodiments, turbomolecular pumps are turned off in the measurement side of the wafer stage so that an exhaust flow can be guided to an exposure side of the wafer stage. In some embodiments, the speed of voltage rise to the electrodes of the wafer chuck is adjusted.Type: ApplicationFiled: August 7, 2023Publication date: November 23, 2023Inventors: Tao-Hsin CHEN, Li-Jui CHEN, Chia-Yu LEE
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Patent number: 11740564Abstract: A method comprises loading a wafer onto a wafer chuck of a lithography apparatus, projecting an extreme ultraviolet light through an opening of a frame structure of the lithography apparatus, onto the wafer, and introducing an airflow from an air curtain module on the wafer chuck toward the frame structure, wherein the air curtain module surrounds the wafer. The airflow forms an air curtain around the wafer, and shields the wafer from contaminants from the frame structure or a wafer stage.Type: GrantFiled: February 2, 2021Date of Patent: August 29, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tao-Hsin Chen, Chia-Yu Lee
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Patent number: 11486052Abstract: Provides an electropolishing treatment method for a stainless steel workpiece, wherein the method comprises the following steps: placing the stainless steel workpiece in an oxalic acid solution and performing supersonic oscillation; performing a first electropolishing treatment to the stainless steel workpiece, wherein the first electropolishing treatment uses the stainless steel workpiece as an anode and 10% to 15% perchloric acid as an electrolyte, and when a constant voltage is set as 12V, the first electropolishing treatment procedure is performed; and performing a second electropolishing treatment to the stainless steel workpiece, wherein the second electropolishing treatment uses the stainless steel workpiece after the first electropolishing treatment as an anode, and an electrolyte consists of ethanol, sulfuric acid and perchloric acid, and when a constant voltage is set as 12V, the second electropolishing treatment is performed to obtain the stainless steel workpiece after the second electropolishingType: GrantFiled: December 27, 2021Date of Patent: November 1, 2022Assignee: NATIONAL CHUNG SHAN INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Chun-Hsiang Kao, Yi-Cherng Ferng, Kuo-Kuang Jen, Shun-Yi Jian, Ming-Hsien Lin, Yu-Chih Tzeng, Chia-Yu Lee
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Publication number: 20220205128Abstract: Provides an electropolishing treatment method for a stainless steel workpiece, wherein the method comprises the following steps: placing the stainless steel workpiece in an oxalic acid solution and performing supersonic oscillation; performing a first electropolishing treatment to the stainless steel workpiece, wherein the first electropolishing treatment uses the stainless steel workpiece as an anode and 10% to 15% perchloric acid as an electrolyte, and when a constant voltage is set as 12V, the first electropolishing treatment procedure is performed; and performing a second electropolishing treatment to the stainless steel workpiece, wherein the second electropolishing treatment uses the stainless steel workpiece after the first electropolishing treatment as an anode, and an electrolyte consists of ethanol, sulfuric acid and perchloric acid, and when a constant voltage is set as 12V, the second electropolishing treatment is performed to obtain the stainless steel workpiece after the second electropolishingType: ApplicationFiled: December 27, 2021Publication date: June 30, 2022Inventors: CHUN-HSIANG KAO, YI-CHERNG FERNG, KUO-KUANG JEN, SHUN-YI JIAN, MING-HSIEN LIN, YU-CHIH TZENG, CHIA-YU LEE
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Publication number: 20220100105Abstract: An EUV lithographic apparatus includes a wafer stage and a particle removing assembly for cleaning a wafer for an extreme ultraviolet (EUV) lithographic apparatus. The wafer stage includes a measurement side and an exposure side. The particle removing assembly includes particle removing electrodes, an exhaust device and turbomolecular pumps. The particle removing electrodes is configured to direct debris from the chamber by suppressing turbulence such that the debris can be exhausted from the wafer stage to the outside of the processing apparatus. In some embodiments, turbomolecular pumps are turned off in the measurement side of the wafer stage so that an exhaust flow can be guided to an exposure side of the wafer stage. In some embodiments, the speed of voltage rise to the electrodes of the wafer chuck is adjusted.Type: ApplicationFiled: October 18, 2021Publication date: March 31, 2022Inventors: Tao-Hsin CHEN, Li-Jui CHEN, Chia-Yu LEE
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Patent number: 11221562Abstract: In some embodiments, a reticle structure is provided. The reticle structure includes a reticle stage and a reticle mounted on the reticle stage. The reticle stage includes plural first burls and plural second burls, in which the second burls are disposed on a center of the reticle stage and the first burls disposed on an edge of the reticle stage such that the first burls surround the second burls. The reticle includes a base material and a pattern layer overlying the base material. The base material is secured on the first and second burls of the reticle stage. The pattern layer includes plural first gratings, and each of the first burls is vertically aligned with one of the first gratings.Type: GrantFiled: March 14, 2019Date of Patent: January 11, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Yu Lee, Tao-Hsin Chen, Ching-Juinn Huang, Po-Chung Cheng
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Publication number: 20210397102Abstract: A method comprises loading a wafer onto a wafer chuck of a lithography apparatus, projecting an extreme ultraviolet light through an opening of a frame structure of the lithography apparatus, onto the wafer, and introducing an airflow from an air curtain module on the wafer chuck toward the frame structure, wherein the air curtain module surrounds the wafer. The airflow forms an air curtain around the wafer, and shields the wafer from contaminants from the frame structure or a wafer stage.Type: ApplicationFiled: February 2, 2021Publication date: December 23, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tao-Hsin CHEN, Chia-Yu LEE
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Patent number: 11150564Abstract: An EUV lithographic apparatus includes a wafer stage and a particle removing assembly for cleaning a wafer for an extreme ultraviolet (EUV) lithographic apparatus. The wafer stage includes a measurement side and an exposure side. The particle removing assembly includes particle removing electrodes, an exhaust device and turbomolecular pumps. The particle removing electrodes is configured to direct debris from the chamber by suppressing turbulence such that the debris can be exhausted from the wafer stage to the outside of the processing apparatus. In some embodiments, turbomolecular pumps are turned off in the measurement side of the wafer stage so that an exhaust flow can be guided to an exposure side of the wafer stage. In some embodiments, the speed of voltage rise to the electrodes of the wafer chuck is adjusted.Type: GrantFiled: September 29, 2020Date of Patent: October 19, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tao-Hsin Chen, Li-Jui Chen, Chia-Yu Lee
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Publication number: 20200292932Abstract: In some embodiments, a reticle structure is provided. The reticle structure includes a reticle stage and a reticle mounted on the reticle stage. The reticle stage includes plural first burls and plural second burls, in which the second burls are disposed on a center of the reticle stage and the first burls disposed on an edge of the reticle stage such that the first burls surround the second burls. The reticle includes a base material and a pattern layer overlying the base material. The base material is secured on the first and second burls of the reticle stage. The pattern layer includes plural first gratings, and each of the first burls is vertically aligned with one of the first gratings.Type: ApplicationFiled: March 14, 2019Publication date: September 17, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Yu LEE, Tao-Hsin CHEN, Ching-Juinn HUANG, Po-Chung CHENG
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Patent number: 10663871Abstract: A reticle stage is provided, including an electrostatic chuck and an acoustic wave transducer. The electrostatic chuck includes multiple chucking electrodes embedded in a dielectric body and configured to secure a reticle to a chuck surface of the dielectric body by electrostatic attraction. The acoustic wave transducer is disposed on the chuck surface and configured to impart a surface acoustic wave to the chuck surface to vibrate the chuck surface, thereby removing the reticle from the reticle stage.Type: GrantFiled: March 20, 2019Date of Patent: May 26, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Yu Lee, Tao-Hsin Chen, Chia-Hao Hsu, Ching-Juinn Huang, Po-Chung Cheng
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Publication number: 20200033717Abstract: A reticle stage is provided, including an electrostatic chuck and an acoustic wave transducer. The electrostatic chuck includes multiple chucking electrodes embedded in a dielectric body and configured to secure a reticle to a chuck surface of the dielectric body by electrostatic attraction. The acoustic wave transducer is disposed on the chuck surface and configured to impart a surface acoustic wave to the chuck surface to vibrate the chuck surface, thereby removing the reticle from the reticle stage.Type: ApplicationFiled: March 20, 2019Publication date: January 30, 2020Inventors: Chia-Yu LEE, Tao-Hsin CHEN, Chia-Hao HSU, Ching-Juinn HUANG, Po-Chung CHENG
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Publication number: 20190144748Abstract: A Cu—MoTi etching solution is provided. The Cu—MoTi etching solution includes 5 to 30 wt % of an oxidant, 3 to 15 wt % of an acid, 3 to 15 wt % of an inorganic salt, and the balance deionized water. The oxidant is selected from hydrogen peroxide or persulfuric acid. The acid is selected from polycarboxylic acids, amino acids, or inorganic acids. The inorganic salt is selected from diammonium hydrogen phosphate or ammonium dihydrogen phosphate.Type: ApplicationFiled: November 24, 2017Publication date: May 16, 2019Inventors: Yue WU, Shan Li, Chunsheng JIANG, Chia-Yu Lee
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Patent number: 9857604Abstract: A stereoscopic display comprises a flat-panel display and an optical layer disposed thereon. The optical layer further includes a lens array layer and a micro-structure layer. The flat-panel display has a display plane. The lens array layer has a base and a plurality of lens with focusing function. The lens array layer adjusts the light field. The micro-structure layer connects to the lens array layer, and includes a substrate and a plurality of micro structures. The micro-structure layer modulates the direction of light so that a stereo image which allows an oblique angle of view natural to the user is displayed.Type: GrantFiled: January 9, 2017Date of Patent: January 2, 2018Assignee: CHERAY CO. LTD.Inventors: Chun-Hsiang Yang, Yi-Pai Huang, Chih-Hung Ting, Ping-Yen Chou, Chih-Wei Shih, Jui-Yi Wu, Chia-Yu Lee
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Publication number: 20170219838Abstract: A stereoscopic display comprises a flat-panel display and an optical layer disposed thereon. The optical layer further includes a lens array layer and a micro-structure layer. The flat-panel display has a display plane. The lens array layer has a base and a plurality of lens with focusing function. The lens array layer adjusts the light field. The micro-structure layer connects to the lens array layer, and includes a substrate and a plurality of micro structures. The micro-structure layer modulates the direction of light so that a stereo image which allows an oblique angle of view natural to the user is displayed.Type: ApplicationFiled: January 9, 2017Publication date: August 3, 2017Inventors: CHUN-HSIANG YANG, YI-PAI HUANG, CHIH-HUNG TING, PING-YEN CHOU, CHIH-WEI SHIH, JUI-YI WU, CHIA-YU LEE
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Patent number: 9386301Abstract: The present invention discloses a stereoscopic display system, which includes a phase retarder, a display panel, a detector unit, and a processing unit. The phase retarder has a plurality of first strip shapes and a plurality of second strip shapes. The first strip shapes and the second strip shapes are alternately arranged. The display panel has a plurality of pixels. The pixels are arranged into a plurality of pixel rows corresponding to the first strip shapes and the second strip shapes. The detector unit utilized to detect a position of an observer's eyes relative to the display panel. The processing unit is electrically coupled to the display panel and the detector unit, and is utilized to adjust a position of the images displayed on the plurality of pixel rows, thereby reducing a crosstalk phenomenon.Type: GrantFiled: June 8, 2012Date of Patent: July 5, 2016Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventor: Chia-Yu Lee
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Patent number: 9240518Abstract: A light emitting diode device is provided, which comprises a silicon-based substrate, a buffer layer, a super lattice structure layer, a nano-structure layer, a first semiconductor layer, a light emitting layer, and a second semiconductor layer. The buffer layer is formed on the silicon-based substrate, the super lattice structure layer is formed on the buffer layer, the nano-structure layer is formed on the super lattice structure layer, a first semiconductor layer is formed on the nano-structure layer, and the light emitting layer is formed between the first semiconductor layer and the second semiconductor layer. The super lattice layer and the nano-structure can release the stress within the light emitting diode device, and reduce the epitaxy defect, so that the internal quantum effect and the external quantum effect can be increased.Type: GrantFiled: August 18, 2014Date of Patent: January 19, 2016Assignee: National Chiao Tung UniversityInventors: Chia-Yu Lee, Da-Wei Lin, An-Jye Tzou, Hao-Chung Kuo
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Publication number: 20150287879Abstract: A light emitting diode device is provided, which comprises a silicon-based substrate, a buffer layer, a super lattice structure layer, a nano-structure layer, a first semiconductor layer, a light emitting layer, and a second semiconductor layer. The buffer layer is formed on the silicon-based substrate, the super lattice structure layer is formed on the buffer layer, the nano-structure layer is formed on the super lattice structure layer, a first semiconductor layer is formed on the nano-structure layer, and the light emitting layer is formed between the first semiconductor layer and the second semiconductor layer. The super lattice layer and the nano-structure can release the stress within the light emitting diode device, and reduce the epitaxy defect, so that the internal quantum effect and the external quantum effect can be increased.Type: ApplicationFiled: August 18, 2014Publication date: October 8, 2015Inventors: Chia-Yu LEE, Da-Wei LIN, An-Jye TZOU, Hao-Chung KUO