Patents by Inventor Chia-Yu Lin
Chia-Yu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240154215Abstract: An aluminum plastic film for a lithium battery and a method for manufacturing the same are provided. The method includes steps as follows: preparing a polyolefin adhesive; coating the polyolefin adhesive onto one surface of an aluminum foil layer; disposing an inner polyolefin layer onto the polyolefin adhesive; and drying the polyolefin adhesive, so that a polyolefin adhesive layer is formed between the aluminum foil layer and the inner polyolefin layer. Components of the polyolefin adhesive include a modified polyolefin polymer and a hardener. The modified polyolefin polymer has a modified group, a structure of the modified group contains maleic anhydride, and a molecular weight of the modified polyolefin polymer ranges from 100,000 g/mol to 200,000 g/mol.Type: ApplicationFiled: February 17, 2023Publication date: May 9, 2024Inventors: TE-CHAO LIAO, SHIOU-YEH SHENG, TENG-KO MA, CHING-YAO YUAN, Chao-Hsien Lin, CHIA-YU LIN, YUN-BIN HSI, HAN-YI LEE, SHUN-CHIEH YANG
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Publication number: 20240153842Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.Type: ApplicationFiled: January 4, 2024Publication date: May 9, 2024Inventors: Hao-Jan Pei, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Cheng-Ting Chen, Chia-Lun Chang, Chih-Wei Lin, Hsiu-Jen Lin, Ching-Hua Hsieh, Chung-Shi Liu
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Publication number: 20240147506Abstract: Apparatus and methods are provided for dynamic sidelink (SL) resource allocation. In one novel aspect, one or more uplink (UL) resources are allocated for SL transceiving. In one embodiment, the UE establishes an SL connection with an SL peer UE, receives an allocation indication indicating one or more UL resources are available as shared SL resources for SL transceiving, wherein the allocation indication is originated from a gNB, and performs SL data transceiving with the SL peer UE using the one or more UL resources indicated in the allocation indication. In one embodiment, the UE receives the allocation indication through the Uu connection by unicast, multicast or broadcast. In one embodiment, the shared SL resources are indicated by RB ID or by SL grants. In one embodiment, conditions for using the shared SL resources are included in the allocation indication or are indicated in a separate RRC configuration.Type: ApplicationFiled: October 12, 2023Publication date: May 2, 2024Inventors: Guan-Yu Lin, Chia-Hao Yu
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Publication number: 20240146462Abstract: Apparatus and methods are provided for relay-assisted retransmission. In one novel aspect, the remote UE receives data transmission from the source entity through a direct link and retransmission from a relay UE. In one embodiment, the relay UE receives feedback indication from the remote UE, transmits the feedback to the source entity, and retransmits one or more TBs to the remote UE through a SL connection upon detecting one or assisted retransmission triggers. In one embodiment, the feedback is a joint HARQ, wherein a NACK is sent when both the relay UE and remote UE failed, and an ACK is sent when at least one of the relay UE and the remote UE succeeds. In one embodiment, the relay UE retransmits one or more successfully received TBs to the remote UE upon receiving a failure indication from the remote UE or receiving retransmission indication from the source entity.Type: ApplicationFiled: October 12, 2023Publication date: May 2, 2024Inventors: Guan-Yu Lin, Chia-Hao Yu
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Publication number: 20240143750Abstract: A case tampering detection device, used for a computer system covered with a computer case, includes at least one detector for detecting whether the computer case is opened and generating a detection result; a storage unit; a microcontroller unit, coupled to the storage unit, for generating a case tampering event and storing the case tampering event in the microcontroller unit or the storage unit when being powered; and a power supply unit, coupled to the at least one detector, for receiving the detection result, and supplying power to the microcontroller unit when the detection result indicates that the computer case is opened.Type: ApplicationFiled: December 8, 2022Publication date: May 2, 2024Applicant: Moxa Inc.Inventors: Yoong Tak TAN, Chia-Te CHOU, Jian-Yu LIAO, Tsung-Yi LIN
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Patent number: 11973050Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes an interconnect structure overlying a semiconductor substrate and comprising a conductive wire. A passivation structure overlies the interconnect structure. An upper conductive structure overlies the passivation structure and comprises a first conductive layer, a dielectric layer, and a second conductive layer. The first conductive layer is disposed between the dielectric layer and the passivation structure. The second conductive layer extends along a top surface of the dielectric layer and penetrates through the first conductive layer and the passivation structure to the conductive wire.Type: GrantFiled: June 2, 2021Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Yu Lin, Yao-Wen Chang, Chia-Wen Zhong, Yen-Liang Lin
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Patent number: 11973039Abstract: A semiconductor device package includes a semiconductor die, a first conductive element, a second conductive element, a metal layer, and a first redistribution layer (RDL). The semiconductor die includes a first surface and a second surface opposite to the first surface. The first conductive element is disposed on the second surface of the semiconductor die. The second conductive element is disposed next to the semiconductor die. The metal layer is disposed on the second conductive element and electrically connected to the second conductive element. The first RDL is disposed on the metal layer and electrically connected to the metal layer.Type: GrantFiled: June 1, 2021Date of Patent: April 30, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chia-Hao Sung, Hsuan-Yu Chen, Yu-Kai Lin
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Publication number: 20240138059Abstract: A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a first dielectric layer, pads, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A top surface of the first dielectric layer is higher than an upper surface of each pad. The first metal layer is disposed on a first surface of the first dielectric layer. The second dielectric layer has second openings exposing part of the first metal layer. The second metal layer extends into the second openings and is electrically connected to the first metal layer. The third dielectric layer has third openings exposing part of the second metal layer. The surface treatment layer is disposed on the upper surfaces.Type: ApplicationFiled: November 23, 2022Publication date: April 25, 2024Applicant: Unimicron Technology Corp.Inventors: Kai-Ming Yang, Chia-Yu Peng, Cheng-Ta Ko, Pu-Ju Lin
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Publication number: 20240138063Abstract: A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a plurality of pads, a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A plurality of first openings of the first dielectric layer expose part of the pads, and a first surface of the first dielectric layer is higher upper surfaces of the pads. The solder balls are disposed in a plurality of third openings of the third dielectric layer and are electrically connected to the second metal layer and the carrier. The surface treatment layer is disposed on the upper surfaces, and a top surface of the surface treatment layer is higher than the first surface.Type: ApplicationFiled: November 15, 2022Publication date: April 25, 2024Applicant: Unimicron Technology Corp.Inventors: Ping-Tsung Lin, Kai-Ming Yang, Chia-Yu Peng, Pu-Ju Lin, Cheng-Ta Ko
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Patent number: 11963969Abstract: Provided is a pharmaceutical composition including gastrodin and a use thereof for the prevention or the treatment of amyotrophic lateral sclerosis. The pharmaceutical composition is effective in reducing neuronal axon degeneration and neurofibromin accumulation, improving symptoms of amyotrophic lateral sclerosis and extending life of patients of amyotrophic lateral sclerosis.Type: GrantFiled: September 16, 2022Date of Patent: April 23, 2024Assignee: BUDDHIST TZU CHI MEDICAL FOUNDATIONInventors: Chia-Yu Chang, Shinn-Zong Lin, Hsiao-Chien Ting, Hui-I Yang, Horng-Jyh Harn, Hong-Lin Su, Ching-Ann Liu, Yu-Shuan Chen, Tzyy-Wen Chiou, Tsung-Jung Ho
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Patent number: 11967522Abstract: A method includes depositing an etch stop layer over a first conductive feature, performing a first treatment to amorphize the etch stop layer, depositing a dielectric layer over the etch stop layer, etching the dielectric layer to form an opening, etching-through the etch stop layer to extend the opening into the etch stop layer, and filling the opening with a conductive material to form a second conductive feature.Type: GrantFiled: April 25, 2022Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jyh-Nan Lin, Chia-Yu Wu, Kai-Shiung Hsu, Ding-I Liu
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Patent number: 11966255Abstract: A fixing structure used to connect a display panel to a housing of an electronic device during manufacture of the electronic device includes a fixing member, an auxiliary member spaced apart from the fixing member, and supporting posts disposed between the fixing member and the auxiliary member. The fixing member is to be bonded to the display panel. A projection of an outer edge of the auxiliary member on a plane of the fixing member is outside of an outer edge of the fixing member. The supporting posts and the auxiliary member are removed after the display panel is bonded to the fixing member. A method for assembling the display panel with the fixing structure is also disclosed.Type: GrantFiled: January 26, 2022Date of Patent: April 23, 2024Assignee: Chiun Mai Communication Systems, Inc.Inventors: Chia-Ju Lin, Fu-Hsin Sung, Meng-Yu Chou
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Patent number: 11961770Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.Type: GrantFiled: November 4, 2021Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Han Lin, Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Surendra Kumar Soni, Shou-Wen Kuo, Wu-An Weng, Gary Tsai, Chien-Ko Liao, Ya Hsun Hsueh, Becky Liao, Ethan Yu, Ming-Chi Tsai, Kuo-Yi Liu
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Publication number: 20240120844Abstract: A resonant flyback power converter includes: a first and a second transistors which form a half-bridge circuit for switching a transformer and a resonant capacitor to generate an output voltage; a current-sense device for sensing a switching current of the half-bridge circuit to generate a current-sense signal; and a switching control circuit generating a first and a second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal controls the half-bridge circuit to generate a positive current to magnetize the transformer and charge the resonant capacitor. The turn-on of the second driving signal controls the half-bridge circuit to generate a negative current to discharge the resonant capacitor. The switching control circuit turns off the first transistor when the positive current exceeds a positive-over-current threshold, and/or, turns off the second transistor when the negative current exceeds a negative-over-current threshold.Type: ApplicationFiled: April 10, 2023Publication date: April 11, 2024Inventors: Kun-Yu LIN, Ta-Yung YANG, Yu-Chang CHEN, Hsin-Yi WU, Fu-Ciao SYU, Chia-Hsien YANG
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Publication number: 20240108592Abstract: Provided is a method for treating cancer by administering to a subject in need thereof with a pharmaceutical composition including a benzenesulfonamide derivative in combination with a cancer immunotherapeutic agent such as the immune check point inhibitor (ICI).Type: ApplicationFiled: September 19, 2023Publication date: April 4, 2024Applicant: Gongwin Biopharm Co., LtdInventors: Shun-Chi WU, Chuan-Ching YANG, Zong-Yu YANG, Chia-En LIN, Mao-Yuan LIN
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Publication number: 20240105642Abstract: A method of manufacturing a package structure at least includes the following steps. An encapsulant laterally is formed to encapsulate the die and the plurality of through vias. A plurality of first connectors are formed to electrically connect to first surfaces of the plurality of through vias. A warpage control material is formed over the die, wherein the warpage control material is disposed to cover an entire surface of the die. A protection material is formed over the encapsulant and around the plurality of first connectors and the warpage control material. A coefficient of thermal expansion of the protection material is less than a coefficient of thermal expansion of the encapsulant.Type: ApplicationFiled: November 29, 2023Publication date: March 28, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Jan Pei, Ching-Hua Hsieh, Hsiu-Jen Lin, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Jen-Jui Yu, Cheng-Shiuan Wong
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Patent number: 11942464Abstract: In an embodiment, a method includes: aligning a first package component with a second package component, the first package component having a first region and a second region, the first region including a first conductive connector, the second region including a second conductive connector; performing a first laser shot on a first portion of a top surface of the first package component, the first laser shot reflowing the first conductive connector of the first region, the first portion of the top surface of the first package component completely overlapping the first region; and after performing the first laser shot, performing a second laser shot on a second portion of the top surface of the first package component, the second laser shot reflowing the second conductive connector of the second region, the second portion of the top surface of the first package component completely overlapping the second region.Type: GrantFiled: July 19, 2021Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Jan Pei, Hsiu-Jen Lin, Wei-Yu Chen, Philip Yu-Shuan Chung, Chia-Shen Cheng, Kuei-Wei Huang, Ching-Hua Hsieh, Chung-Shi Liu, Chen-Hua Yu
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Patent number: 11942563Abstract: A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.Type: GrantFiled: June 1, 2023Date of Patent: March 26, 2024Assignee: XINTEC INC.Inventors: Chia-Sheng Lin, Hui-Hsien Wu, Jian-Hong Chen, Tsang-Yu Liu, Kuei-Wei Chen
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Publication number: 20240088062Abstract: A package structure includes a die, an encapsulant laterally encapsulating the die, a warpage control material disposed over the die, and a protection material disposed over the encapsulant and around the warpage control material. A coefficient of thermal expansion of the protection material is less than a coefficient of thermal expansion of the encapsulant.Type: ApplicationFiled: November 23, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Jan Pei, Ching-Hua Hsieh, Hsiu-Jen Lin, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Jen-Jui Yu, Cheng-Shiuan Wong