Abstract: A biocompatible magnetic material containing an iron oxide nanoparticle and one or more biocompatible polymers, each having formula (I) below, covalently bonded to the iron oxide nanoparticle: in which each of variables R, L, x, and y is defined herein, the biocompatible magnetic material contains 4-15% Fe(II) ions relative to the total iron ions. Also disclosed in a method of preparing the biocompatible magnetic material.

Abstract: A programming method of a non-volatile memory cell is provided. The non-volatile memory cell includes a memory transistor. Firstly, a current limiter is provided, and the current limiter is connected between a drain terminal of the memory transistor and a ground terminal. Then, a program voltage is provided to a source terminal of the memory transistor, and a control signal is provided to a gate terminal of the memory transistor. In a first time period of a program action, the control signal is gradually decreased from a first voltage value, so that the memory transistor is firstly turned off and then slightly turned on. When the memory transistor is turned on, plural hot electrons are injected into a charge trapping layer of the memory transistor.

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

Abstract: Gate isolation processes (e.g., gate-to-source/drain contact isolation) are described herein. An exemplary contact gate isolation process may include recessing (e.g., by etching) sidewall portions of a high-k gate dielectric and gate spacers of a gate structure to form a contact gate isolation (CGI) opening that exposes sidewalls of a gate electrode of the gate structure, forming a gate isolation liner along the sidewalls of the gate electrode that partially fills the CGI opening, and forming a gate isolation layer over the gate isolation liner that fills a remainder of the CGI opening. A dielectric constant of the gate isolation liner is less than a dielectric constant of the high-k gate dielectric. A dielectric constant of the gate isolation layer is less than a dielectric constant of the high-k gate dielectric. A dielectric constant of the gate isolation layer may be less than a dielectric constant of the gate isolation layer.

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The method includes forming a metal gate stack wrapped around multiple semiconductor nanostructures. The semiconductor nanostructures are beside an epitaxial structure. The method includes forming a dielectric layer over the metal gate stack and the epitaxial structure. The method further includes forming a contact opening in the dielectric layer and forming a protective layer over sidewalls of the contact opening. In addition, the method includes deepening the contact opening so that the contact opening extends into the epitaxial structure after the formation of the protective layer. The method includes forming a conductive contact filling the contact opening.

Abstract: An integrated circuit includes a nanosheet transistor having a plurality of stacked channels, a gate electrode surrounding the stacked channels, a source/drain region, and a source/drain contact. The integrated circuit includes a first dielectric layer between the gate metal and the source/drain contact, a second dielectric layer on the first dielectric layer, and a cap metal on the first gate metal and on a hybrid fin structure. The second dielectric layer is on the hybrid fin structure between the cap metal and the source/drain contact.

Abstract: An integrated circuit includes a first nanostructure transistor having a first gate electrode and a second nanostructure transistor having a second gate electrode. A dielectric isolation structure is between the first and second gate electrodes. A gate connection metal is on a portion of the top surface of the first gate electrode and on a portion of a top surface of the second gate electrode. The gate connection metal is patterned to expose other portions of the top surfaces of the first and second gate electrodes adjacent to the dielectric isolation structure. A conductive via contacts the exposed portion of the top surface of the second gate electrode.

Abstract: After a friendship pairing process is executed according to a phone directory, send a friendship request message, create at least one first platform identity by the first user, and the first user uses a first platform identity of the at least one first platform identity to make friends with the second user having a platform identity. The first user does not have any platform identity before the first user creates the at least one first platform identity.

Abstract: After a friendship pairing process is executed according to a phone directory, send a friendship request message, create at least one first platform identity by the first user, and the first user uses a first platform identity of the at least one first platform identity to make friends with the second user having a platform identity. The first user does not have any platform identity before the first user creates the at least one first platform identity.

Abstract: The present invention discloses a fixing mechanism for fixing a board card on a circuit board. The fixing mechanism includes a standoff for supporting the board card on the circuit board. A first end of the standoff is fixed inside a hole on the circuit board. A stepping opening is formed on a second end of the standoff, and the second end of the standoff contacts against the board card. The fixing mechanism further includes a blind rivet, a first end of the blind rivet engages inside the stepping opening, and a second end of the blind rivet fastens on the board card so as to fix the board card on the circuit board.

Abstract: An electrode device for a plasma processing system is presented. The electrode device is installed in a chamber of the plasma processing system. The electrode device comprises a plurality of electrode assemblies. Each electrode assembly has at least one first electrode and at least one second electrode. The first electrode is connected to a first output of a power supply, and the second electrode, connected to a second output of the power supply. Each electrode assembly is spaced apart from each other so as to generate plasma in the chamber. The electrode assembly comprises at least two electrodes (the first electrode and the second electrode) with shorter distance between the electrodes, and the type of the power supply can be altered to increase the electric field intensity, the hollow cathode effect, plasma density and uniformity. The electrode device can raise the efficiency in processing the object, and increase the uniformity of the electric field and upgrade the quality of the object.

Abstract: A cleaning device with deeply reaching plasma and assisting electrodes has supporting racks, a chamber, a plasma sources, metallic grids. Flat boards to be cleaned such as circuit boards are located in the supporting racks. The supporting racks are disposed in the chamber. The metallic grids are disposed on two sides of the chamber. The plasma source is disposed next to the metallic grids. Electric voltage is applied to the metallic grids such that plasma from the plasma source can be pushed deeply into the supporting racks to evenly and sufficiently clean the circuit boards.

Abstract: A cleaning device with deeply reaching plasma and assisting electrodes has supporting racks, a chamber, a plasma sources, metallic grids. Flat boards to be cleaned such as circuit boards are located in the supporting racks. The supporting racks are disposed in the chamber. The metallic grids are disposed on two sides of the chamber. The plasma source is disposed next to the metallic grids. Electric voltage is applied to the metallic grids such that plasma from the plasma source can be pushed deeply into the supporting racks to evenly and sufficiently clean the circuit boards.

Abstract: A cleaning device with deeply reaching plasma and assisting electrodes has supporting racks, a chamber, a plasma sources, metallic grids. Flat boards to be cleaned such as circuit boards are located in the supporting racks. The supporting racks are disposed in the chamber. The metallic grids are disposed on two sides of the chamber. The plasma source is disposed next to the metallic grids. Electric voltage is applied to the metallic grids such that plasma from the plasma source can be pushed deeply into the supporting racks to evenly and sufficiently clean the circuit boards.

Abstract: A cleaning device with deeply reaching plasma and assisting electrodes has supporting racks, a chamber, a plasma. sources, metallic grids. Flat boards to be cleaned such as circuit boards are located in the supporting racks. The supporting racks are disposed in the chamber. The metallic grids are disposed on two sides of the chamber. The plasma source is disposed next to the metallic grids. Electric voltage is applied to the metallic grids such that plasma from the plasma source can be pushed deeply into the supporting racks to evenly and sufficiently clean the circuit boards.