Abstract: Computer implemented techniques for the partitioned simulation of parallel architectures are disclosed. A high-level design for simulation is obtained. A graph representation for the high-level design is determined. The graph for the high-level design is partitioned into sub-graphs. A subset of the sub-graphs is selected for simulation based on input-change bits of the sub-graphs. The subset of the sub-graphs is subsequently evaluated on parallel architectures in order to produce a simulation result for the high-level design.

Abstract: Computer implemented techniques for the partitioned simulation of parallel architectures are disclosed. A high-level design for simulation is obtained. A graph representation for the high-level design is determined. The graph for the high-level design is partitioned into sub-graphs. A subset of the sub-graphs is selected for simulation based on input-change bits of the sub-graphs. The subset of the sub-graphs is subsequently evaluated on parallel architectures in order to produce a simulation result for the high-level design.

Abstract: In one embodiment, a plurality of kernels are provided. Each kernel may simulate a partition of a design under test. A plurality of event regions are provided. The regions may be in an ordered priority. Events for the device under test may be determined for event regions in each of the kernels. An event region to execute events in is then determined and all kernels may execute events in the same event region. Kernels then execute events for the determined event region. When finished executing events in an event queue, data synchronization may occur. In this case, information may be synced among kernels, such as status and state values for shared objected are synchronized.

Abstract: Computer implemented techniques for the partitioned simulation of parallel architectures are disclosed. A high-level design for simulation is obtained. A graph representation for the high-level design is determined. The graph for the high-level design is partitioned into sub-graphs. A subset of the sub-graphs is selected for simulation based on input-change bits of the sub-graphs. The subset of the sub-graphs is subsequently evaluated on parallel architectures in order to produce a simulation result for the high-level design.

Abstract: In one embodiment, a plurality of kernels are provided. Each kernel may simulate a partition of a design under test. A plurality of event regions are provided. The regions may be in an ordered priority. Events for the device under test may be determined for event regions in each of the kernels. An event region to execute events in is then determined and all kernels may execute events in the same event region. Kernels then execute events for the determined event region. When finished executing events in the event queue, data synchronization may occur. In this case, information may be synced among kernels, such as status and state values for shared objected are synchronized.

Abstract: To identify a finite state machine and verify a circuit design, the invention identifies, in a design description, a set of constructs, a construct in the set of constructs, and an object in the construct. It next identifies a first subset of constructs in the set of constructs which can control a change of a value of the object, and then identifies a second subset of constructs whose values can be changed directly or indirectly by the object. The identifying and storing steps are repeated for all objects in the construct and for all constructs in the set of constructs. A finite state machine is identified by searching for a first object which controls a change of a value of a second object and whose value is also changed directly or indirectly by the second object. This method of identifying finite state machine elements in a design description is used by a test generator which then generates test vectors for exercising the finite state machine elements on a test bench.

Abstract: The speed of a hardware-software debugger is markedly increased through the use of high speed simulators which ignore all systems operations except those where design errors are expected to manifest themselves, by skipping CPU bus cycles of no interest for the simulation, by not explicitly simulating periodic clock signals and generating only schedules of clock signals, and by caching instructions when alien computers are used in the simulation process to eliminate decoding of the instructions of the target computer.