Patents by Inventor Chiajen M. Lee

Chiajen M. Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods, systems, and devices for offset compensation in CMOC imagers
    Patent number: 7872676
    Abstract: Methods, devices, and systems for offset compensation in an amplifier are disclosed, wherein the amplifier inputs may be exposed to large loads from an array of pixel columns coupled in parallel. During a sampling phase, an amplifier offset may be sampled by selectively coupling a first amplifier output to a first amplifier input and a second amplifier output to a second amplifier input. During a portion of the sampling phase, the first amplifier output may be buffered to a first storage element. During a different portion of the sampling phase, the second amplifier output may be buffered to a second storage element. To sense the pixel columns during an amplification phase, the first storage element and the second storage element are coupled to the first and second amplifier inputs, respectively, with the result that the amplifier offset is canceled from the amplifier output.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: January 18, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Espen A. Olsen, Chiajen M. Lee, Christopher Zeleznik
  • METHODS, SYSTEMS, AND DEVICES FOR OFFSET COMPENSATION IN CMOS IMAGERS
    Publication number: 20090015692
    Abstract: Methods, devices, and systems for offset compensation in an amplifier are disclosed, wherein the amplifier inputs may be exposed to large loads from an array of pixel columns coupled in parallel. During a sampling phase, an amplifier offset may be sampled by selectively coupling a first amplifier output to a first amplifier input and a second amplifier output to a second amplifier input. During a portion of the sampling phase, the first amplifier output may be buffered to a first storage element. During a different portion of the sampling phase, the second amplifier output may be buffered to a second storage element. To sense the pixel columns during an amplification phase, the first storage element and the second storage element are coupled to the first and second amplifier inputs, respectively, with the result that the amplifier offset is canceled from the amplifier output.
    Type: Application
    Filed: July 13, 2007
    Publication date: January 15, 2009
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Espen A. Olsen, Chiajen M. Lee, Christopher Zeleznik
  • Method and apparatus for calibrating parallel readout paths in imagers
    Patent number: 7453054
    Abstract: An imaging device with readout chain circuitry that uses multiple analog-to-digital converters and amplifiers, which are similarly calibrated using a stitching technique, to readout each color of a column and mitigate the possibility of a boundary effect.
    Type: Grant
    Filed: August 23, 2005
    Date of Patent: November 18, 2008
    Assignee: Aptina Imaging Corporation
    Inventors: Chiajen M. Lee, Kwang-Bo Cho