Patents by Inventor Chiaki Dono
Chiaki Dono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11581056Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for direct access hybrid testing. A memory device, such as a high bandwidth memory (HBM) may include direct access terminals. During a testing procedure, test instructions may be provided to the memory through the direct access terminals. The test instructions include a data pointer which is associated with one of a plurality of test patterns pre-loaded in the memory and an address. The selected test pattern may be written to, and subsequently read from, the memory cells associated with the address. The read test pattern may be compared to the selected test pattern to generate result information. The test patterns may be loaded to the memory, and the result information may be read out from the memory, in an operational mode different than the operational mode in which the test instructions are provided.Type: GrantFiled: December 16, 2020Date of Patent: February 14, 2023Assignee: Micron Technology, Inc.Inventors: Chiaki Dono, Chikara Kondo, Roman A. Royer
-
Patent number: 11156658Abstract: Techniques for memory I/O tests using integrated test data paths are provided. In an example, a method for operating input/output data paths of a memory apparatus can include receiving, during a first mode, non-test information at a data terminal of a first channel of the memory apparatus from a memory array of the first channel via a first data path, receiving during a first test mode, first test information at the data terminal of the first channel from a first additional data path coupling the first channel with a second channel of the memory apparatus, and wherein an interface die of the memory apparatus includes the first data path and the additional data path.Type: GrantFiled: June 20, 2019Date of Patent: October 26, 2021Assignee: Micron Technology, Inc.Inventor: Chiaki Dono
-
Patent number: 11120849Abstract: Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first semiconductor chip and a second semiconductor chips that are stacked with each other via through substrate vias (TSVs) provided in one of the first semiconductor chip and the second semiconductor chip. The first semiconductor chip and the second semiconductor chips communicate with each other by use of data bus inversion data that have been encoded using a DBI algorithm.Type: GrantFiled: July 1, 2019Date of Patent: September 14, 2021Assignee: Micron Technology, Inc.Inventors: Chikara Kondo, Chiaki Dono
-
Patent number: 11067628Abstract: Disclosed herein are systems, methods, and devices that enable access to a first interface control circuit via test probes of a second interface. In some embodiments a memory device includes a first interface including first ports that are inaccessible to a test probe. The memory device also includes a first interface control circuit configured to control operation of the first interface. The memory device further includes a second interface including second ports. At least a portion of the second ports include test pads that are accessible to the test probe. In addition, the memory device includes a multiplexer configured to operably couple the first interface and at least a portion of the second interface to the first interface control circuit. The multiplexer is configured to selectively enable test probe access to the first interface control circuit via the test pads.Type: GrantFiled: September 20, 2019Date of Patent: July 20, 2021Assignee: Micron Technology, Inc.Inventors: Chiaki Dono, Chikara Kondo, Ryo Fujimaki
-
Publication number: 20210104293Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for direct access hybrid testing. A memory device, such as a high bandwidth memory (HBM) may include direct access terminals. During a testing procedure, test instructions may be provided to the memory through the direct access terminals. The test instructions include a data pointer which is associated with one of a plurality of test patterns pre-loaded in the memory and an address. The selected test pattern may be written to, and subsequently read from, the memory cells associated with the address. The read test pattern may be compared to the selected test pattern to generate result information. The test patterns may be loaded to the memory, and the result information may be read out from the memory, in an operational mode different than the operational mode in which the test instructions are provided.Type: ApplicationFiled: December 16, 2020Publication date: April 8, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Chiaki Dono, Chikara Kondo, Roman A. Royer
-
Publication number: 20210088583Abstract: Disclosed herein are systems, methods, and devices that enable access to a first interface control circuit via test probes of a second interface. In some embodiments a memory device includes a first interface including first ports that are inaccessible to a test probe. The memory device also includes a first interface control circuit configured to control operation of the first interface. The memory device further includes a second interface including second ports. At least a portion of the second ports include test pads that are accessible to the test probe. In addition, the memory device includes a multiplexer configured to operably couple the first interface and at least a portion of the second interface to the first interface control circuit. The multiplexer is configured to selectively enable test probe access to the first interface control circuit via the test pads.Type: ApplicationFiled: September 20, 2019Publication date: March 25, 2021Inventors: Chiaki Dono, Chikara Kondo, Ryo Fujimaki
-
Patent number: 10943625Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described.Type: GrantFiled: December 19, 2019Date of Patent: March 9, 2021Assignee: Micron Technology, Inc.Inventors: Chikara Kondo, Tomoyuki Shibata, Chiaki Dono, Seiji Narui, Minehiko Uehara, Taihei Shido, Homare Sato
-
Patent number: 10937518Abstract: Apparatuses including a test interface circuit that is configured to merge multiple independent traffic streams generated from individual algorithmic pattern generators (APGs) for communication with a memory device over a shared memory interface. The combination of multiple independent traffic streams, each with their own looping sequences and command timings, may generate a large set of random command sequences. The test interface circuit may include an arbiter circuit that merges a first independent traffic stream from a first APG and a second independent traffic stream from a second APG. Each of the first and second independent traffic streams are directed to different semi-independently-accessible portions of the memory device. The memory device may include a hybrid memory cube having independently accessible vaults or a high bandwidth memory device having independently accessible channels, in some examples.Type: GrantFiled: December 12, 2018Date of Patent: March 2, 2021Assignee: Micron Technology, Inc.Inventors: Roman A. Royer, Chikara Kondo, Chiaki Dono
-
Patent number: 10896738Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for direct access hybrid testing. A memory device, such as a high bandwidth memory (HBM) may include direct access terminals. During a testing procedure, test instructions may be provided to the memory through the direct access terminals. The test instructions include a data pointer which is associated with one of a plurality of test patterns pre-loaded in the memory and an address. The selected test pattern may be written to, and subsequently read from, the memory cells associated with the address. The read test pattern may be compared to the selected test pattern to generate result information. The test patterns may be loaded to the memory, and the result information may be read out from the memory, in an operational mode different than the operational mode in which the test instructions are provided.Type: GrantFiled: October 2, 2019Date of Patent: January 19, 2021Assignee: Micron Technology, Inc.Inventors: Chiaki Dono, Chikara Kondo, Roman A. Royer
-
Patent number: 10854310Abstract: Apparatuses and methods for an interface chip that interfaces with chips are described. An example apparatus includes: first terminals; circuit groups, each of the circuit groups including circuit blocks being configured to electrically couple to the first terminals; a control circuit that selects one of the circuit groups and electrically couple the first terminals to the circuit blocks of the one of the circuit groups; terminal groups, each of the terminal groups including second terminals, each of the terminal groups being provided correspondingly to each of the circuit groups, the second terminals of each of the terminal groups being smaller in number than the circuit blocks of a corresponding one of the circuit groups; and a remapping circuit that couples the second terminals of each of the terminal groups to selected ones of the circuit blocks of the corresponding one of the circuit groups.Type: GrantFiled: June 10, 2019Date of Patent: December 1, 2020Assignee: Micron Technology, Inc.Inventors: Chiaki Dono, Taihei Shido, Yuki Ebihara
-
Patent number: 10839889Abstract: Apparatuses and methods for providing clocks to data paths are disclosed. An example apparatus includes a first circuit in a data path, a second circuit in the data path, and a multiplexer. The first circuit is configured to provide data based on a first clock and the second circuit is configured to receive the data and provide the data based on a second clock. The multiplexer is configured to provide a third clock as the second clock for some test operations and further configured to provide the first clock as the second clock for other test operations. A timing of the first clock is adjusted for the first circuit during the test operations.Type: GrantFiled: October 2, 2019Date of Patent: November 17, 2020Assignee: Micron Technology, Inc.Inventors: Hyunui Lee, Chiaki Dono, Chikara Kondo
-
Patent number: 10790039Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip including a data I/O terminal, a test terminal, a first data input node, a first data output node, a read circuit, a write circuit, and a test circuit configured to transfer a test data supplied from the test terminal to the read circuit, and a second semiconductor chip including a second data input node connected to the first data output node, a second data output node connected to the first data input node, and a memory cell array. The test circuit is configured to activate the read circuit, the write circuit and the memory cell array so that the test data is written into the memory cell array via the read circuit, the data I/O terminal, the write circuit, the first data output node, and the second data input node.Type: GrantFiled: September 26, 2019Date of Patent: September 29, 2020Assignee: Micron Technology, Inc.Inventors: Hyunui Lee, Chiaki Dono
-
Publication number: 20200194090Abstract: Apparatuses including a test interface circuit that is configured to merge multiple independent traffic streams generated from individual algorithmic pattern generators (APGs) for communication with a memory device over a shared memory interface. The combination of multiple independent traffic streams, each with their own looping sequences and command timings, may generate a large set of random command sequences. The test interface circuit may include an arbiter circuit that merges a first independent traffic stream from a first APG and a second independent traffic stream from a second APG. Each of the first and second independent traffic streams are directed to different semi-independently-accessible portions of the memory device. The memory device may include a hybrid memory cube having independently accessible vaults or a high bandwidth memory device having independently accessible channels, in some examples.Type: ApplicationFiled: December 12, 2018Publication date: June 18, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Roman A. Royer, Chikara Kondo, Chiaki Dono
-
Patent number: 10636461Abstract: Apparatuses and methods for providing multiphase clock signals are described. An example apparatus includes first, second, third and fourth clocked inverters, first and second clock terminals, and first and second latch circuits. An input node and an output node of the first clocked inverter is coupled respectively to an output node of the fourth clocked inverter and an input node of the second clocked inverter. An input node and an output node of the third clocked inverter is coupled to an output node of the second clocked inverter and an input node of the fourth clocked inverter. The first and second clock terminals are supplied respectively with first and second clock signals. The first latch is coupled between the output nodes of the first and third clocked inverters, and the second latch circuit is coupled between the output nodes of the second and fourth clocked inverters.Type: GrantFiled: March 19, 2019Date of Patent: April 28, 2020Assignee: Micron Technology, Inc.Inventors: Homare Sato, Chiaki Dono, Chikara Kondo
-
Publication number: 20200126603Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described.Type: ApplicationFiled: December 19, 2019Publication date: April 23, 2020Applicant: Micron Technology, Inc.Inventors: Chikara Kondo, Tomoyuki Shibata, Chiaki Dono, Seiji Narui, Minehiko Uehara, Taihei Shido, Homare Sato
-
Patent number: 10553263Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described.Type: GrantFiled: December 19, 2018Date of Patent: February 4, 2020Assignee: Micron Technology, Inc.Inventors: Chikara Kondo, Tomoyuki Shibata, Chiaki Dono, Seiji Narui, Minehiko Uehara, Taihei Shido, Homare Sato
-
Patent number: 10468114Abstract: Apparatuses and methods for an interface chip that interfaces with chips are described. An example apparatus includes: first terminals; circuit groups, each of the circuit groups including circuit blocks being configured to electrically couple to the first terminals; a control circuit that selects one of the circuit groups and electrically couple the first terminals to the circuit blocks of the one of the circuit groups; terminal groups, each of the terminal groups including second terminals, each of the terminal groups being provided correspondingly to each of the circuit groups, the second terminals of each of the terminal groups being smaller in number than the circuit blocks of a corresponding one of the circuit groups; and a remapping circuit that couples the second terminals of each of the terminal groups to selected ones of the circuit blocks of the corresponding one of the circuit groups.Type: GrantFiled: June 20, 2018Date of Patent: November 5, 2019Assignee: Micron Technology, Inc.Inventors: Chiaki Dono, Taihei Shido, Yuki Ebihara
-
Publication number: 20190325926Abstract: Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first semiconductor chip and a second semiconductor chips that are stacked with each other via through substrate vias (TSVs) provided in one of the first semiconductor chip and the second semiconductor chip. The first semiconductor chip and the second semiconductor chips communicate with each other by use of data bus inversion data that have been encoded using a DBI algorithm.Type: ApplicationFiled: July 1, 2019Publication date: October 24, 2019Applicant: Micron Technology, Inc.Inventors: Chikara Kondo, Chiaki Dono
-
Publication number: 20190302181Abstract: Techniques for memory I/O tests using integrated test data paths are provided. In an example, a method for operating input/output data paths of a memory apparatus can include receiving, during a first mode, non-test information at a data terminal of a first channel of the memory apparatus from a memory array of the first channel via a first data path, receiving during a first test mode, first test information at the data terminal of the first channel from a first additional data path coupling the first channel with a second channel of the memory apparatus, and wherein an interface die of the memory apparatus includes the first data path and the additional data path.Type: ApplicationFiled: June 20, 2019Publication date: October 3, 2019Inventor: Chiaki Dono
-
Publication number: 20190295679Abstract: Apparatuses and methods for an interface chip that interfaces with chips are described. An example apparatus includes: first terminals; circuit groups, each of the circuit groups including circuit blocks being configured to electrically couple to the first terminals; a control circuit that selects one of the circuit groups and electrically couple the first terminals to the circuit blocks of the one of the circuit groups; terminal groups, each of the terminal groups including second terminals, each of the terminal groups being provided correspondingly to each of the circuit groups, the second terminals of each of the terminal groups being smaller in number than the circuit blocks of a corresponding one of the circuit groups; and a remapping circuit that couples the second terminals of each of the terminal groups to selected ones of the circuit blocks of the corresponding one of the circuit groups.Type: ApplicationFiled: June 10, 2019Publication date: September 26, 2019Applicant: Micron Technology, Inc.Inventors: Chiaki Dono, Taihei Shido, Yuki Ebihara