Patents by Inventor Chiaki Dono

Chiaki Dono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10373657
    Abstract: Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first semiconductor chip and a second semiconductor chips that are stacked with each other via through substrate vias (TSVs) provided in one of the first semiconductor chip and the second semiconductor chip. The first semiconductor chip and the second semiconductor chips communicate with each other by use of data bus inversion data that have been encoded using a DBI algorithm.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: August 6, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Chikara Kondo, Chiaki Dono
  • Patent number: 10365325
    Abstract: Techniques for memory I/O tests using integrated test data paths are provided. In an example, a method for operating input/output data paths of a memory apparatus can include receiving, during a first mode, non-test information at a data terminal of a first channel of the memory apparatus from a memory array of the first channel via a first data path, receiving during a first test mode, first test information at the data terminal of the first channel from a first additional data path coupling the first channel with a second channel of the memory apparatus, and wherein an interface die of the memory apparatus includes the first data path and the additional data path.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: July 30, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Chiaki Dono
  • Publication number: 20190214061
    Abstract: Apparatuses and methods for providing multiphase clock signals are described. An example apparatus includes first, second, third and fourth clocked inverters, first and second clock terminals, and first and second latch circuits. An input node and an output node of the first clocked inverter is coupled respectively to an output node of the fourth clocked inverter and an input node of the second clocked inverter. An input node and an output node of the third clocked inverter is coupled to an output node of the second clocked inverter and an input node of the fourth clocked inverter. The first and second clock terminals are supplied respectively with first and second clock signals. The first latch is coupled between the output nodes of the first and third clocked inverters, and the second latch circuit is coupled between the output nodes of the second and fourth clocked inverters.
    Type: Application
    Filed: March 19, 2019
    Publication date: July 11, 2019
    Inventors: Homare Sato, Chiaki Dono, Chikara Kondo
  • Patent number: 10338997
    Abstract: An apparatus includes a first external terminal, a first circuit, a signal line and a second circuit. The first external terminal receives at least one of data mask information and data bus inversion information. The first circuit performs one of an error check operation and a data bus inversion operation. The signal line is coupled between the first external terminal and the first circuit. The second circuit is coupled to the signal line and first a voltage level of the signal line at a substantially constant level responsive to a first control signal.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: July 2, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Chiaki Dono, Seiichi Maruno, Taihei Shido, Toshio Ninomiya, Chikara Kondo
  • Publication number: 20190122708
    Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described.
    Type: Application
    Filed: December 19, 2018
    Publication date: April 25, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Chikara Kondo, Tomoyuki Shibata, Chiaki Dono, Seiji Narui, Minehiko Uehara, Taihei Shido, Homare Sato
  • Publication number: 20190115057
    Abstract: Apparatuses and methods for providing multiphase clock signals are described. An example apparatus includes first, second, third and fourth clocked inverters, first and second clock terminals, and first and second latch circuits. An input node and an output node of the first clocked inverter is coupled respectively to an output node of the fourth clocked inverter and an input node of the second clocked inverter. An input node and an output node of the third clocked inverter is coupled to an output node of the second clocked inverter and an input node of the fourth clocked inverter. The first and second dock terminals are supplied respectively with first and second clock signals. The first latch is coupled between the output nodes of the first and third clocked inverters, and the second latch circuit is coupled between the output nodes of the second and fourth clocked inverters.
    Type: Application
    Filed: October 13, 2017
    Publication date: April 18, 2019
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Homare Sato, Chiaki Dono, Chikara Kondo
  • Patent number: 10262704
    Abstract: Apparatuses and methods for providing multiphase clock signals are described. An example apparatus includes first, second, third and fourth clocked inverters, first and second clock terminals, and first and second latch circuits. An input node and an output node of the first clocked inverter is coupled respectively to an output node of the fourth clocked inverter and an input node of the second clocked inverter. An input node and an output node of the third clocked inverter is coupled to an output node of the second clocked inverter and an input node of the fourth clocked inverter. The first and second clock terminals are supplied respectively with first and second clock signals. The first latch is coupled between the output nodes of the first and third clocked inverters, and the second latch circuit is coupled between the output nodes of the second and fourth clocked inverters.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: April 16, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Homare Sato, Chiaki Dono, Chikara Kondo
  • Publication number: 20190066816
    Abstract: Techniques for memory I/O tests using integrated test data paths are provided. In an example, a method for operating input/output data paths of a memory apparatus can include receiving, during a first mode, non-test information at a data terminal of a first channel of the memory apparatus from a memory array of the first channel via a first data path, receiving during a first test mode, first test information at the data terminal of the first channel from a first additional data path coupling the first channel with a second channel of the memory apparatus, and wherein an interface die of the memory apparatus includes the first data path and the additional data path.
    Type: Application
    Filed: August 22, 2017
    Publication date: February 28, 2019
    Inventor: Chiaki Dono
  • Patent number: 10163469
    Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: December 25, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Chikara Kondo, Tomoyuki Shibata, Chiaki Dono, Seiji Narui, Minehiko Uehara, Taihei Shido, Homare Sato
  • Publication number: 20180301202
    Abstract: Apparatuses and methods for an interface chip that interfaces with chips are described. An example apparatus includes: first terminals; circuit groups, each of the circuit groups including circuit blocks being configured to electrically couple to the first terminals; a control circuit that selects one of the circuit groups and electrically couple the first terminals to the circuit blocks of the one of the circuit groups; terminal groups, each of the terminal groups including second terminals, each of the terminal groups being provided correspondingly to each of the circuit groups, the second terminals of each of the terminal groups being smaller in number than the circuit blocks of a corresponding one of the circuit groups; and a remapping circuit that couples the second terminals of each of the terminal groups to selected ones of the circuit blocks of the corresponding one of the circuit groups.
    Type: Application
    Filed: June 20, 2018
    Publication date: October 18, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Chiaki Dono, Taihei Shido, Yuki Ebihara
  • Publication number: 20180293128
    Abstract: An apparatus includes a first external terminal, a first circuit, a signal line and a second circuit. The first external terminal receives at least one of data mask information and data bus inversion information. The first circuit performs one of an error check operation and a data bus inversion operation. The signal line is coupled between the fist external terminal and the first circuit. The second circuit is coupled to the signal line and first a voltage level of the signal line at a substantially constant level responsive to a first control signal.
    Type: Application
    Filed: May 17, 2018
    Publication date: October 11, 2018
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Chiaki Dono, Seiichi Maruno, Taihei Shido, Toshio Ninomiya, Chikara Kondo
  • Patent number: 10008287
    Abstract: Apparatuses and methods for an interface chip are described. An example apparatus includes a first chip. The first chip includes, on a single semiconductor substrate, first terminals, circuit groups, and terminal groups corresponding to the circuit groups, each of the circuit groups including circuit blocks. A control circuit in the first chip selects one of the circuit groups and electrically couples the first terminals to the circuit blocks of the selected circuit group. Second terminals are included in each of the terminal groups. A number of all of the second terminals in each of the terminal groups is smaller than a number of all of the circuit blocks in the corresponding circuit group. The first chip further includes, for example, a remapping circuit.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: June 26, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Chiaki Dono, Taihei Shido, Yuki Ebihara
  • Publication number: 20180151207
    Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described.
    Type: Application
    Filed: November 30, 2016
    Publication date: May 31, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Chikara Kondo, Tomoyuki Shibata, Chiaki Dono, Seiji Narui, Minehiko Uehara, Taihei Shido, Homare Sato
  • Patent number: 9983925
    Abstract: A control circuit receives the mode signals supplied from a mode register and a read enable signal READ supplied from a control logic circuit, which activates enable signals EN1 to EN3 based on the mode signals and read enable signal. For example, the read enable signal READ is activated when a read command is issued from the controller. One mode signal can indicate an operation mode in which a multi-purpose register is used, and another mode signal can indicate an operation mode in which the data bus inversion function is used. When a data masking operation is disabled and an error check operation is enabled, the mode register activates a protection signal SEL. When the data masking operation is enabled or the error check operation is disabled, the protection signal SEL is deactivated. The operation of a deserializer is controlled by clock signals and the protection signal SEL.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: May 29, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Chiaki Dono, Seiichi Maruno, Taihei Shido, Toshio Ninomiya, Chikara Kondo
  • Publication number: 20180047432
    Abstract: Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first semiconductor chip and a second semiconductor chips that are stacked with each other via through substrate vias (TSVs) provided in one of the first semiconductor chip and the second semiconductor chip. The first semiconductor chip and the second semiconductor chips communicate with each other by use of data bus inversion data that have been encoded using a DBI algorithm.
    Type: Application
    Filed: August 10, 2016
    Publication date: February 15, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Chikara Kondo, Chiaki Dono
  • Publication number: 20180025789
    Abstract: Apparatuses and methods for an interface chip that interfaces with chips are described. An example apparatus includes: first terminals; circuit groups, each of the circuit groups including circuit blocks being configured to electrically couple to the first terminals; a control circuit that selects one of the circuit groups and electrically couple the first terminals to the circuit blocks of the one of the circuit groups; terminal groups, each of the terminal groups including second terminals, each of the terminal groups being provided correspondingly to each of the circuit groups, the second terminals of each of the terminal groups being smaller in number than the circuit blocks of a corresponding one of the circuit groups; and a remapping circuit that couples the second terminals of each of the terminal groups to selected ones of the circuit blocks of the corresponding one of the circuit groups.
    Type: Application
    Filed: July 22, 2016
    Publication date: January 25, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Chiaki Dono, Taihei Shido, Yuki Ebihara
  • Patent number: 9412432
    Abstract: A semiconductor storage device is provided with a memory cell array comprising a plurality of word lines including word lines that are adjacent to one another; and a TRR address conversion unit that selects the word line in response to the input of an address signal indicating a first value while in a first operation mode and selects the word line in response to the input of an address signal indicating a first value while in a target row refresh mode. Due to the fact that address conversion is performed on the semiconductor storage device side in the present invention, it is sufficient for a control device to output, for example, the address of a word line having a high access count to the semiconductor storage device during a target row refresh operation. As a result, control of the target row refresh operation on the control device side is facilitated.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: August 9, 2016
    Assignee: PS4 LUXCO S.A.R.L.
    Inventors: Seiji Narui, Hiromasa Noda, Chiaki Dono, Chikara Kondo, Masayuki Nakamura
  • Publication number: 20160042782
    Abstract: [Problem] To regenerate the charge of a memory cell having reduced information retention characteristics using a target row refresh operation. [Solution] A semiconductor storage device is provided with a memory cell array (11) comprising a plurality of word lines including word lines (WLI, WL2) that are adjacent to one another; and a TRR address conversion unit (53) that selects the word line (WL1) in response to the input of an address signal (IADD) indicating a first value while in a first operation mode and selects the word line (WL2) in response to the input of an address signal indicating a first value while in a target row refresh mode. Due to the fact that address conversion is performed on the semiconductor storage device side in the present invention, it is sufficient for a control device to output, for example, the address of a word line having a high access count to the semiconductor storage device during a target row refresh operation.
    Type: Application
    Filed: March 13, 2014
    Publication date: February 11, 2016
    Inventors: Seiji Narui, Hiromasa Noda, Chiaki Dono, Chikara Kondo, Masayuki Nakamura
  • Publication number: 20160034340
    Abstract: An apparatus includes a first external terminal, a first circuit, a signal line and a second circuit, The first external terminal receives at least one of data mask information and data bus inversion information. The first circuit performs one of an error check operation and as data bus invasion operation. The signal line is coupled between the first external terminal and the first circuit. The second circuit is coupled to the signal line and first a voltage level of the signal line at a substantially constant level responsive to a first control signal.
    Type: Application
    Filed: April 3, 2015
    Publication date: February 4, 2016
    Inventors: CHIAKI DONO, Seiichi Maruno, Taihei Shido, Toshio Ninomiya, Chikara Kondo
  • Patent number: 9130556
    Abstract: Disclosed herein is a device that includes a first buffer circuit coupled between a first power supply line and a data terminal and a second buffer circuit coupled between a second power supply line and the data terminal. First and second internal data signals complementary to each other are supplied to a level shifter, thereby third and fourth internal data signals complementary to each other are generated by changing amplitude values of the first and second internal data signals. The first and the second buffer circuits are controlled based on the third and fourth internal data signals such that one of the first and second buffer circuits turns on and the other of the first and second buffer circuits turns off.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 8, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Chiaki Dono, Takenori Sato, Shinya Miyazaki