Abstract: A decoder circuit includes p-channel MOS transistors P.sub.1 and P.sub.2, n-channel MOS transistors N.sub.1 to N.sub.4 having gates to which data signals D.sub.1 to D.sub.4 are inputted, respectively, an n-channel MOS transistor N.sub.s connected in series to the n-channel MOS transistors N.sub.1 to N.sub.4 and having a gate to which the precharging signal .PHI. is inputted, and an n-channel MOS transistor N.sub.5 connected between P.sub.2 and N.sub.1. In the decoder circuit, the gate of N.sub.5 is connected to the drain of P.sub.2, and a capacity C.sub.H is connected between the gate of N.sub.5 and a power potential. In a holding state, the power potential is held by the aid of the capacity C.sub.H connected to the gate of N.sub.5.