Abstract: A semiconductor device includes: an isolation region formed in a semiconductor substrate; an active region surrounded by the isolation region; and a first gate electrode formed on the isolation region and the active region and including a first region on the isolation region. The first region has a pattern width in a gate length direction larger than a pattern width of the first gate electrode on the active region. The first region includes a part having a film thickness different from a film thickness of the first gate electrode on the active region.

Abstract: When charges Q (x, y) transferred from an image inputting device 1 are to be converted into first signal intensities S? (x, y) and signal processing is to be performed for the first signal intensity S? (x, y) of a particular pixel, a maximum value Smax, a minimum value Smin and an average value Save are calculated from signal intensities S? (x?1, y) and S? (x+1, y) at adjacent pixels. When S? (x, y)>Smax×A is satisfied, it is determined that the signal intensity S (x, y) at the particular pixel=Save×C (where A and C are coefficients), whereas when S? (x, y)<Smin×B is satisfied, it is determined that the signal intensity S (x, y)=Save×D (where B and D are coefficients), and processing is performed so as to obtain an appropriate intensity S (x, y). This makes it possible to accurately judge a defective pixel attributable to dirt adhering to a pixel array of the image inputting device, a crystal defect, etc., and compensate a defect in an image caused by the defective pixel.

Abstract: The following steps are carried out: forming a gate electrode on a semiconductor substrate with a gate insulating film interposed therebetween, forming a dummy gate electrode on the semiconductor substrate with a dummy gate insulating film interposed therebetween and forming another dummy gate electrode on the semiconductor substrate with an insulating film for isolation interposed therebetween; forming a metal film on the semiconductor while exposing the gate electrode and covering the dummy gate electrodes; and subjecting the semiconductor substrate to heat treatment and thus siliciding at least an upper part of the gate electrode. Since the gate electrode is silicided and the dummy gate electrodes are non-silicided, this restrains a short circuit from being caused between the gate electrode and adjacent one of the dummy gate electrodes.

Abstract: A semiconductor device includes an active region and a dummy active region formed in a semiconductor substrate to have a distance from each other, an isolation region formed between the active region and the dummy active region and has a top surface lower than top surfaces of the active region and the dummy active region, a gate insulating film formed on the active region and a fully silicided gate electrode formed on the isolation region, the gate insulating film and the dummy active region through full silicidation of a silicon gate material film with metallic material.

Abstract: A semiconductor device includes a MIS transistor having a gate electrode which is fully silicided with metal. The edge parts of the gate electrode are lower in height than the other part thereof. Sidewall spacers are formed to cover the side and top surfaces of the edge parts of the gate electrode.

Abstract: A semiconductor device includes a first conductor and a second conductor electrically connected to each other to have the same potential. At least one of the first and second conductors has a fully silicided (FUSI) structure. A step having an overhang is formed at least at part of a boundary between the first and second conductors.

Abstract: A semiconductor device includes: an isolation region formed in a semiconductor substrate; an active region surrounded by the isolation region; and a first gate electrode formed on the isolation region and the active region and including a first region on the isolation region. The first region has a pattern width in a gate length direction larger than a pattern width of the first gate electrode on the active region. The first region includes a part having a film thickness different from a film thickness of the first gate electrode on the active region.

Abstract: The following steps are carried out: forming a gate electrode on a semiconductor substrate with a gate insulating film interposed therebetween, forming a dummy gate electrode on the semiconductor substrate with a dummy gate insulating film interposed therebeweeen and forming another dummy gate electrode on the semiconductor substrate with an insulating film for isolation interposed therebetween; forming a metal film on the semiconductor while exposing the gate electrode and covering the dummy gate electrodes; and subjecting the semiconductor substrate to heat treatment and thus siliciding at least an upper part of the gate electrode. Since the gate electrode is silicided and the dummy gate electrodes are non-silicided, this restrains a short circuit from being caused between the gate electrode and adjacent one of the dummy gate electrodes.

Abstract: A semiconductor device includes a MIS transistor formed in a region of a semiconductor region. The MIS transistor includes a gate insulating film formed on the region, a gate electrode formed on the gate insulating film and fully silicided with metal, source/drain regions formed in parts of the region on the sides of the gate electrode and an insulating film formed to cover the gate electrode and the source/drain regions to cause stress strain in part of the region below the gate electrode.

Abstract: In a semiconductor device including a MIS transistor with a FUSI gate electrode and a polysilicon resistor, a portion of the polysilicon resistor provided in a contact formation region is silicided simultaneously with the gate electrode or an impurity diffusion region.

Abstract: A semiconductor device includes a first field-effect transistor including a first gate electrode and a second field-effect transistor including a second gate electrode. The first gate electrode and the second gate electrode are integrated using a connecting portion and are fully silicided with a metal in such a manner that the fist and second gate electrodes have different metal contents. A diffusion preventing film for preventing the metal from diffusing between the first and second gate electrodes is formed in at least a portion of the connecting portion.

Abstract: A semiconductor device includes a first MIS transistor including a first gate electrode fully silicided with a metal. With the first MIS transistor includes: a first gate insulating film formed on a semiconductor region; the first gate electrode formed on the first gate insulating film; a first sidewall spacer formed on a side of the first gate electrode; and a second sidewall spacer formed at the side of the first gate electrode with the first sidewall spacer interposed therebetween; the first sidewall spacer and the second sidewall spacer have different etching characteristics. The first sidewall spacer has an upper end lower than an upper surface of the first gate electrode and an upper end of the second sidewall spacer.

Abstract: In an interconnection mask pattern generation, there are suppressed a decrease in reliability of an interconnection and a decrease in manufacture yield, which are resulted from use of an interconnection pattern generated with single minimum line width data for a semiconductor device or the like. When a layout interconnection pattern on a mask for an interconnection which connects functional elements to each other being arranged based on logical circuit data is generated, an interconnection pattern based on the minimum line width data is generated, an interconnection pattern based on the minimum line spacing data is also generated, and an interconnection pattern arranging a new interconnection boundary in the middle of both of them is then generated to be used as a final interconnection pattern, so that the interconnection pattern width becomes properly thick in width, thereby making it possible to improve reliability of the interconnection and suppress a decrease in manufacturing yield.

Abstract: When charges Q (x, y) transferred from an image inputting device 1 are to be converted into first signal intensities S? (x, y) and signal processing is to be performed for the first signal intensity S? (x, y) of a particular pixel, a maximum value Smax, a minimum value Smin and an average value Save are calculated from signal intensities S? (x?1, y) and S? (x+1, y) at adjacent pixels. When S? (x, y)>Smax×A is satisfied, it is determined that the signal intensity S (x, y) at the particular pixel=Save×C (where A and C are coefficients), whereas when S? (x, y)<Smin×B is satisfied, it is determined that the signal intensity S (x, y)=Save×D (where B and D are coefficients), and processing is performed so as to obtain an appropriate intensity S (x, y). This makes it possible to accurately judge a defective pixel attributable to dirt adhering to a pixel array of the image inputting device, a crystal defect, etc., and compensate a defect in an image caused by the defective pixel.

Abstract: In an interconnection mask pattern generation, there are suppressed a decrease in reliability of an interconnection and a decrease in manufacture yield, which are resulted from use of an interconnection pattern generated with single minimum line width data for a semiconductor device or the like. When a layout interconnection pattern on a mask for an interconnection which connects functional elements to each other being arranged based on logical circuit data is generated, an interconnection pattern based on the minimum line width data is generated, an interconnection pattern based on the minimum line spacing data is also generated, and an interconnection pattern arranging a new interconnection boundary in the middle of both of them is then generated to be used as a final interconnection pattern, so that the interconnection pattern width becomes properly thick in width, thereby making it possible to improve reliability of the interconnection and suppress a decrease in manufacturing yield.

Abstract: On a semiconductor substrate of P-type silicon, an active area including a channel forming region with a smaller dimension along the gate width and a source region and a drain region extending along the gate length is formed so as to be surrounded with an isolation area of an insulating oxide film. On the isolation area on the semiconductor substrate and the channel forming region of the active area, a gate electrode is formed with a gate insulating oxide film sandwiched therebetween. A channel lower insulating layer is formed, out of the same insulating oxide film for the isolation area, merely in an area below the channel forming region below the gate electrode in the active area of the semiconductor substrate.

Abstract: The top surface of a P-type semiconductor substrate is partitioned into an active region to be formed with an element and an isolation region surrounding the active region. The isolation region is composed of trench portions and dummy semiconductor portions. An interlayer insulating film is deposited on the substrate, followed by a wire formed thereon. In each of the semiconductor portions, an impurity diffusion layer is formed simultaneously with the implantation of ions into the element so that a PN junction is formed between the impurity diffusion layer and the silicon substrate. A capacitance component of the wiring-to-substrate capacitance in the region containing the semiconductor portions is obtained by adding in series the capacitance in the impurity diffusion layer to the capacitance in the interlayer insulating film, which is smaller than the capacitance only in the interlayer insulating film.

Abstract: The top surface of a P-type semiconductor substrate is partitioned into an active region to be formed with an element and an isolation region surrounding the active region. The isolation region is composed of trench portions and dummy semiconductor portions. An interlayer insulating film is deposited on the substrate, followed by a wire formed thereon. In each of the semiconductor portions, an impurity diffusion layer is formed simultaneously with the implantation of ions into the element so that a PN junction is formed between the impurity diffusion layer and the silicon substrate. A capacitance component of the wiring-to-substrate capacitance in the region containing the semiconductor portions is obtained by adding in series the capacitance in the impurity diffusion layer to the capacitance in the interlayer insulating film, which is smaller than the capacitance only in the inter layer insulating film.

Abstract: On a semiconductor substrate of P-type silicon, an active area including a channel forming region with a smaller dimension along the gate width and a source region and a drain region extending along the gate length is formed so as to be surrounded with an isolation area of an insulating oxide film. On the isolation area on the semiconductor substrate and the channel forming region of the active area, a gate electrode is formed with a gate insulating oxide film sandwiched therebetween. A channel lower insulating layer is formed, out of the same insulating oxide film for the isolation area, merely in an area below the channel forming region below the gate electrode in the active area of the semiconductor substrate.

Abstract: A MOS capacitor has a p-type silicon substrate, an n-type impurity diffusion area formed by implanting an impurity into a region of the silicon substrate, a silicon oxide layer formed on the diffusion area, and a polysilicon electrode formed on the silicon oxide layer. An impurity profile is formed in the region such that the concentration of the impurity increases from a surface common to the diffusion area and the silicon oxide layer towards the inside of the silicon substrate. The concentration of the impurity at the interface is less than or equal to 1.times.10.sup.20 cm.sup.-3, and a peak concentration lies at a depth of more than 0.05 .mu.m under the interface. This controls accelerated oxidization during the thermal oxidization and also controls the dependence of the capacitance on the voltage.