Abstract: A composition having excellent curability and adhesive bonding ability is provided. A composition, comprising the following components (1) to (5): (1) a polymerizable vinyl monomer containing 10 to 70 parts by mass of (1-1), 10 to 60 parts by mass of (1-2), and 10 to 60 parts by mass of (1-3) based on 100 parts by mass of (1) the polymerizable vinyl monomer, in which (1-1) is a (meth)acrylic monomer represented by the formula (A) Formula (A) Z—O—R1 (wherein, Z represents a (meth)acryloyl group, and R1 represents an alkyl group.

Abstract: A curable composition containing a polymerizable compound (A) and a polymerization initiator (B). A half width of a temperature-loss tangent (tan ?) graph is 90° C. or higher and 150° C. or lower, where the half width is obtained by measuring a dynamic viscoelasticity of a cured substance of this curable composition under measurement conditions of frequency: 1.0 Hz, mode: tensile mode, measurement temperature range: ?50° C. to 200° C., and temperature rising rate: 2° C./min.

Abstract: An imaging device includes a controller, a power supply, a regulator, and a switch. The controller is configured to control an imaging unit, on the basis of a command and data that are received from a host in accordance with an I2C/I3C communication protocol. The power supply is configured to supply a voltage to a digital block of the controller. The digital block is configured to be subjected to dynamic voltage frequency scaling within one-frame operation. The regulator and the switch are provided between the digital block and the power supply, and coupled in parallel with each other.

Abstract: An imaging device includes a controller, a power supply, a regulator, and a switch. The controller is configured to control an imaging unit, on the basis of a command and data that are received from a host in accordance with an I2C/I3C communication protocol. The power supply is configured to supply a voltage to a digital block of the controller. The digital block is configured to be subjected to dynamic voltage frequency scaling within one-frame operation. The regulator and the switch are provided between the digital block and the power supply, and coupled in parallel with each other.

Abstract: An imaging device includes a controller and a generator. The controller controls an imaging unit on the basis of a command and data received from a host in accordance with an I2C/I3C communication protocol. The generator generates a second control signal indicating whether or not to apply intra-frame dynamic frequency scaling (DFS) or intra-frame dynamic voltage frequency scaling (DVFS) on the basis of a first control signal received from the host via a first route different from the I2C/I3C communication protocol, and outputs the second control signal to the host via a second route different from the I2C/I3C communication protocol.

Abstract: An imaging device includes a controller and a generator. The controller controls an imaging unit on the basis of a command and data received from a host in accordance with an I2C/I3C communication protocol. The generator generates a second control signal indicating whether or not to apply intra-frame dynamic frequency scaling (DFS) or intra-frame dynamic voltage frequency scaling (DVFS) on the basis of a first control signal received from the host via a first route different from the I2C/I3C communication protocol, and outputs the second control signal to the host via a second route different from the I2C/I3C communication protocol.

Abstract: A composition having excellent curability and adhesive bonding ability is provided. A composition, comprising the following components (1) to (5): (1) a polymerizable vinyl monomer containing 10 to 70 parts by mass of (1-1), 10 to 60 parts by mass of (1-2), and 10 to 60 parts by mass of (1-3) based on 100 parts by mass of (1) the polymerizable vinyl monomer, in which (1-1) is a (meth)acrylic monomer represented by the formula (A) Formula (A) Z—O—R1 (wherein, Z represents a (meth)acryloyl group, and R1 represents an alkyl group.

Abstract: Methods and apparatus provide for: a plurality of stages of combinational logic, each stage including a full latch circuit operable to transfer data into the given stage of combinational logic and a transparent latch circuit operable transfer output data from the given stage of combinational logic to a next of the stages; in each stage, passing state changes of output data from the given combinational logic irrespective of when such changes occur when a clock signal of the transparent latch circuit is at a first of two logic levels; and in each stage, withholding state changes of the output data until the clock signal of the transparent latch circuit transitions from the second of the two logic levels to the first logic level.

Abstract: Methods and apparatus for distributing a clock signal to a digital circuit provide for: producing a clock signal; and delaying, advanced, or leaving the clock signal unchanged to produce an output clock signal as a function of a control signal, wherein an amount of delay or advancement between the clock signal and the output clock signal (phase difference) is a function of time variant changes in a magnitude of a power supply voltage to the digital circuit.

Abstract: Processors arranged in a multi-processor configuration for substantially parallel operations receive their initialization data in order to start operations, such as graphics computations, real-time multimedia streaming, etc. Due to a change in the processing load, one or more processors might be deactivated. Subsequently, the load increases to such a level that requires all or some of the deactivated processors to be active again. In this case, the boot-up process of the entire system is not carried out as it would be time-consuming and wasteful; instead, responsive to a control signal only those processors that were previously in inactive mode are re-initialized by selecting a configuration data supplied by another processor, controller or any other intelligent programmable device.

Abstract: Methods and apparatus for distributing a clock signal to a digital circuit provide for: producing a clock signal; and delaying, advanced, or leaving the clock signal unchanged to produce an output clock signal as a function of a control signal, wherein an amount of delay or advancement between the clock signal and the output clock signal (phase difference) is a function of time variant changes in a magnitude of a power supply voltage to the digital circuit.

Abstract: Methods and apparatus for distributing clock signals to an integrated circuit provide for: producing, in a slow mode of operation, a first clock signal having at least first and second on-pulses of differing first and second on-times each period, respectively, where a sum of the first and second on-times is approximately equal to a sum of off-times each period; distributing the first clock signal through a distribution tree and terminating at a plurality of final buffer circuits that produce respective distributed clock signals from which respective second clock signals are produced to supply at least a portion of the integrated circuit; deleting the second on-pulse from each of the distributed clock signals each period to produce the respective second clock signals, the second clock signals each including at least a portion of the first on-pulse, but none of the second on-pulse each period.

Abstract: Methods and apparatus for distributing clock signals to an integrated circuit provide for: producing, in a slow mode of operation, a first clock signal having at least first and second on-pulses of differing first and second on-times each period, respectively, where a sum of the first and second on-times is approximately equal to a sum of off-times each period; distributing the first clock signal through a distribution tree and terminating at a plurality of final buffer circuits that produce respective distributed clock signals from which respective second clock signals are produced to supply at least a portion of the integrated circuit; deleting the second on-pulse from each of the distributed clock signals each period to produce the respective second clock signals, the second clock signals each including at least a portion of the first on-pulse, but none of the second on-pulse each period.

Abstract: Methods and apparatus for dynamically (AC) testing a target circuit within a main circuit include: providing respective sets of input latches from among a plurality of latches of the main circuit; reconfiguring connections of at least some of the input latches from normal connections within the main circuit such that each set of input latches is connected in series and directs an input bit stream from an associated source node into an associated input node of the target circuit; scanning a plurality of sets of input bits into the respective sets of input latches such that each latch of each set of input latches contains a respective bit of an associated one of the sets of input bits; and scanning each of the sets of input bits serially into the respective input nodes of the target circuit at a sufficiently high frequency to dynamically test the target circuit.

Abstract: An apparatus and method are disclosed which may include a multiple-stage inverter circuit, having at least first, second, and third stages, wherein a ratio (Rm-(m-1)) between a size of a given one of said stages “m” to a size of a stage “m-1” immediately preceding stage m is less than N(1/L-1), where “L” equals the number of stages in said inverter circuit and “N” equals the size ratio between the last and first stages of the inverter circuit.

Abstract: Processors arranged in a multi-processor configuration for substantially parallel operations receive their initialization data in order to start operations, such as graphics computations, real-time multimedia streaming, etc. Due to a change in the processing load, one or more processors might be deactivated. Subsequently, the load increases to such a level that requires all or some of the deactivated processors to be active again. In this case, the boot-up process of the entire system is not carried out as it would be time-consuming and wasteful; instead, responsive to a control signal only those processors that were previously in inactive mode are re-initialized by selecting a configuration data supplied by another processor, controller or any other intelligent programmable device.

Abstract: An apparatus is disclosed which includes a signal generator providing a first signal having a first frequency; a clock tree operative to propagate the first signal to at least one clock mesh of the apparatus; and a final buffer operative to receive the first signal, provide a second signal having a second frequency, synchronize the second signal with the first signal, and propagate the synchronized second signal to at least one other clock mesh of the apparatus.

Abstract: Methods and apparatus provide for: producing a control signal at a first substantially steady state logic level indicative of a sleep mode, and at a second substantially steady state logic level indicative of a normal mode; producing a gate signal that is at a substantially steady state null level when the control signal is at the first logic level, and that oscillates at a local clock frequency when the control signal is at the second logic level; producing a local clock signal from a system clock signal as a function of the gate signal; and interposing at least one signal propagation latch circuit between an origin of the control signal and the location at which the gate signal is produced.

Abstract: Methods and apparatus provide for: producing a control signal at a first substantially steady state logic level indicative of a sleep mode, and at a second substantially steady state logic level indicative of a normal mode; producing a gate signal that is at a substantially steady state null level when the control signal is at the first logic level, and that oscillates at a local clock frequency when the control signal is at the second logic level; producing a local clock signal from a system clock signal as a function of the gate signal; and interposing at least one signal propagation latch circuit between an origin of the control signal and the location at which the gate signal is produced.

Abstract: An apparatus is disclosed which includes a signal generator providing a first signal having a first frequency; a clock tree operative to propagate the first signal to at least one clock mesh of the apparatus; and a final buffer operative to receive the first signal, provide a second signal having a second frequency, synchronize the second signal with the first signal, and propagate the synchronized second signal to at least one other clock mesh of the apparatus.