Abstract: The present invention relates to an information processing apparatus, an information processing method, and a program capable of simplifying an interrupt processing and reducing a time necessary to the interrupt processing. An interrupt generation unit 140 generates an interrupt signal. An interrupt status holding unit 142 stores an interrupt status showing a cause of generation of the interrupt signal. An interrupt status supply unit 141 supplies an interrupt status stored by an interrupt status holding unit to a RAM and causes the RAM to store it. A CPU executes a predetermined processing in response to the interrupt status stored to the RAM. The present invention can be applied to, for example, a network card.

Abstract: The present invention relates to an information processing apparatus, an information processing method and a program for simplifying an interrupt process to reduce time needed for the interrupt process. If it is determined in step S52 that a network card pointer and a CPU clear pointer fail to match each other, i.e., that there is a packet area corresponding to a packet used in an executed DMA transfer process and having not undergone a DMA transfer complete process, processing proceeds to step S53. An interrupt generator sets a completion status as an interrupt status and proceeds to step S54. In step S54, the interrupt generator generates an interrupt signal. If it is determined in step S52 that there is not a packet area corresponding to a packet used in an executed DMA transfer process and having not undergone a DMA transfer complete process, processing proceeds to step S55. The interrupt generator clears the completion status. The present invention is applicable to a network card, for example.

Abstract: An information processing device is provided. The information processing device includes a frame acquiring unit for acquiring a frame using a signal transmitted via a network, a computing unit for computing a check sequence on the basis of data included in the frame, a checking unit for checking whether the frame is corrupted by checking whether the check sequence coincides with a check sequence added to the frame in advance, a storing unit for storing a table that is a list of check sequences computed in advance on the basis of a plurality of pieces of data representing addresses of frames to be received by the information processing device, and a determining unit for determining whether the frame should be received by determining whether a check sequence computed by the computing unit on the basis of data representing a destination address of the frame coincides with any one of the check sequences included in the table.

Abstract: An information processing apparatus is provided. Plural processors respectively execute separate operating systems to process data that has been received from a network. The apparatus includes receiving device that receives the data in predetermined units from the network and analyzing device that analyzes identification data added to the data received by the receiving device. The apparatus also includes maintaining device which maintains a table that relates the identification data to information on identification of an interrupt register in each of the processors that execute the operating systems. The apparatus further includes interrupting device that allows interrupt processing to any of the processors to occur by writing the data received with the receiving device into the interrupt register that is related to the identification data, which is identified on the based of the table maintained by the maintaining device, analyzed by the analyzing device.

Abstract: The present invention relates to an information processing apparatus, an information processing method and a program for simplifying an interrupt process to reduce time needed for the interrupt process. If it is determined in step S52 that a network card pointer and a CPU clear pointer fail to match each other, i.e., that there is a packet area corresponding to a packet used in an executed DMA transfer process and having not undergone a DMA transfer complete process, processing proceeds to step S53. An interrupt generator sets a completion status as an interrupt status and proceeds to step S54. In step S54, the interrupt generator generates an interrupt signal. If it is determined in step S52 that there is not a packet area corresponding to a packet used in an executed DMA transfer process and having not undergone a DMA transfer complete process, processing proceeds to step S55. The interrupt generator clears the completion status. The present invention is applicable to a network card, for example.

Abstract: An information processor includes: generating section generating a descriptor, the descriptor including positional information, which indicates a packet-by-packet recording position of the data in the memory, and delay time relating to packet-by-packet processing; an extracting section acquiring the descriptor generated by the generating section and extracting the positional information and the delay time from the acquired descriptor; an DMA section reading packet-by-packet data from the memory on the basis of the extracted positional information; and a delaying section delaying processing of at least one of the extracting section and the DMA section by the delay time that has been extracted by the extracting section.

Abstract: The present invention relates to an information processing apparatus, an information processing method, and a program capable of simplifying an interrupt processing and reducing a time necessary to the interrupt processing. An interrupt generation unit 140 generates an interrupt signal. An interrupt status holding unit 142 stores an interrupt status showing a cause of generation of the interrupt signal. An interrupt status supply unit 141 supplies an interrupt status stored by an interrupt status holding unit to a RAM and causes the RAM to store it. A CPU executes a predetermined processing in response to the interrupt status stored to the RAM. The present invention can be applied to, for example, a network card.

Abstract: An information processing device is provided. The information processing device includes a frame acquiring unit for acquiring a frame using a signal transmitted via a network, a computing unit for computing a check sequence on the basis of data included in the frame, a checking unit for checking whether the frame is corrupted by checking whether the check sequence coincides with a check sequence added to the frame in advance, a storing unit for storing a table that is a list of check sequences computed in advance on the basis of a plurality of pieces of data representing addresses of frames to be received by the information processing device, and a determining unit for determining whether the frame should be received by determining whether a check sequence computed by the computing unit on the basis of data representing a destination address of the frame coincides with any one of the check sequences included in the table.

Abstract: An information processing apparatus is provided. Plural processors respectively execute separate operating systems to process data that has been received from a network. The apparatus includes receiving device that receives the data in predetermined units from the network and analyzing device that analyzes identification data added to the data received by the receiving device. The apparatus also includes maintaining device which maintains a table that relates the identification data to information on identification of an interrupt register in each of the processors that execute the operating systems. The apparatus further includes interrupting device that allows interrupt processing to any of the processors to occur by writing the data received with the receiving device into the interrupt register that is related to the identification data, which is identified on the based of the table maintained by the maintaining device, analyzed by the analyzing device.

Abstract: An information processor includes: generating section generating a descriptor, the descriptor including positional information, which indicates a packet-by-packet recording position of the data in the memory, and delay time relating to packet-by-packet processing; an extracting section acquiring the descriptor generated by the generating section and extracting the positional information and the delay time from the acquired descriptor; an DMA section reading packet-by-packet data from the memory on the basis of the extracted positional information; and a delaying section delaying processing of at least one of the extracting section and the DMA section by the delay time that has been extracted by the extracting section.