Abstract: Aspects of the disclosure provide a source device that includes a first encoder and a second encoder. The first encoder is configured to generate an encoded message by encoding an original message using a fixed-length code that has a fixed code rate. The second encoder is configured to generate a parity code by encoding the encoded message using a variable-length code that has an adjustable code rate set based on a requested code rate. Aspects of the disclosure further provide a destination device that includes a mixer and a decoder. The mixer is configured to generate a reconstructed message by decoding an incoming message and a parity code using a variable-length code that has an adjustable code rate. The decoder is configured to decode the reconstructed message using a fixed-length code that has a fixed code rate.

Abstract: A turbo decoder includes a plurality of decoder cores arranged for parallel decoding of a plurality of code segments of a code block in an iteration. Each of the decoder cores is arranged to decode a corresponding code segment according to a sliding window having a window size smaller than a length of the corresponding code segment in most cases, and sequentially generate a plurality of decoded soft outputs each derived from decoding an encoded soft input selected from the corresponding code segment by the sliding window.

Abstract: A decoding apparatus has an on-chip buffer, an external buffer interface, and a turbo decoder. The on-chip buffer is arranged for buffering each code block to be decoded. The external buffer interface is arranged for accessing an off-chip buffer. The turbo decoder is arranged for decoding a specific code block read from the on-chip buffer. The specific code block is not transmitted from the on-chip buffer to the off-chip buffer via the external buffer interface unless decoding fail of the specific code block is identified.

Abstract: A decoding apparatus includes a memory device and a decoding circuit. The memory device is arranged for storing a data block with inter-row interleaving in a plurality of data rows of the data block and without intra-row interleaving in each of the data rows. The decoding circuit is coupled to the memory device. The decoding circuit is arranged for accessing the memory device to perform a first decoding operation with inter-row de-interleaving memory access, and accessing the memory device to perform a second decoding operation with intra-row de-interleaving memory access.

Abstract: A decoding apparatus has an on-chip buffer, an external buffer interface, and a turbo decoder. The on-chip buffer is arranged for buffering each code block to be decoded. The external buffer interface is arranged for accessing an off-chip buffer. The turbo decoder is arranged for decoding a specific code block read from the on-chip buffer. The specific code block is not transmitted from the on-chip buffer to the off-chip buffer via the external buffer interface unless decoding fail of the specific code block is identified.

Abstract: A turbo decoder includes a plurality of decoder cores arranged for parallel decoding of a plurality of code segments of a code block in an iteration. Each of the decoder cores is arranged to decode a corresponding code segment according to a sliding window having a window size smaller than a length of the corresponding code segment in most cases, and sequentially generate a plurality of decoded soft outputs each derived from decoding an encoded soft input selected from the corresponding code segment by the sliding window.

Abstract: A method includes, during a first iteration of a first decoder for decoding convolutionally encoded data elements, determining a first value of a first path metric. The method also includes, during a second iteration of the first decoder, determining a second value of the first path metric by using the first value of the first path metric as an initial value of the first path metric.

Abstract: A decoding apparatus includes a memory device and a decoding circuit. The memory device is arranged for storing a data block with inter-row interleaving in a plurality of data rows of the data block and without intra-row interleaving in each of the data rows. The decoding circuit is coupled to the memory device. The decoding circuit is arranged for accessing the memory device to perform a first decoding operation with inter-row de-interleaving memory access, and accessing the memory device to perform a second decoding operation with intra-row de-interleaving memory access memory access.

Abstract: A system and method is provided for improved and efficient decoding of a received data sequence. The invention can perform the decoding using a LogMap function for a set of N inputs, where N is greater than 2.

Abstract: A method includes, during a first iteration of a first decoder for decoding convolutionally encoded data elements, determining a first value of a first path metric. The method also includes, during a second iteration of the first decoder, determining a second value of the first path metric by using the first value of the first path metric as an initial value of the first path metric.

Abstract: A system and method is provided for improved and efficient forward and backward recursive computations that may be used, for example, with turbo code decoding applications. The invention performs the forward computations using a full length of a sequence to be decoded and performs the reverse computations using a sliding window over the sequence.

Abstract: A system and method is provided for improved and efficient forward and backward recursive computations that may be used, for example, with turbo code decoding applications. The invention performs the forward computations using a full length of a sequence to be decoded and performs the reverse computations using a sliding window over the sequence.

Abstract: A multiple stage matched filter for a wireless receiver comprises a receiver configured to develop a received signal, the received signal comprising a bit stream of signal samples, and a multiple stage matched filter configured to parallel process the received signal such that multiple codes are analyzed simultaneously to determine a frequency offset and code location.

Abstract: A device, such as an interleaver, a de-interleaver, or other devices, for interleaving or de-interleaving a signal within a wireless communication system. The device may interleave or de-interleave the signal spontaneously using a pseudo-random logic. Interleaving or de-interleaving the signal spontaneously may enable one or more features of the device to be enhanced. For example, less RAM may be required to interleave or de-interleave the signal, a die size of the device may be decreased, or other features may be enhanced. The device may receive a signal including a plurality of symbols. The plurality of symbols may be organized into one or more symbol blocks. While a number of symbols in the symbol blocks may vary from block to block, all (or substantially all) of the symbol blocks may be augmented to be of a fixed block length. Dummy bits may be used to augment the symbol blocks.

Abstract: A system and method is provided for improved and efficient forward and backward recursive computations that may be used, for example, with turbo code decoding applications. The invention performs the forward computations using a full length of a sequence to be decoded and performs the reverse computations using a sliding window over the sequence.

Abstract: A multiple stage matched filter for a wireless receiver comprises a receiver configured to develop a received signal, the received signal comprising a bit stream of signal samples, and a multiple stage matched filter configured to parallel process the received signal such that multiple codes are analyzed simultaneously to determine a frequency offset and code location.

Abstract: A system and method for information content-independent synchronization with a received signal. A variable of the signal (e.g., average energy or magnitude) which is related to the energy distribution, is measured over a period of time. The signal's information bearing point is found at the point within the information period of the signal with the highest averaged energy. The point may be found, for example, by detecting the sample point with highest average energy, or by correlating multiple sample points to a stored template. Interpolation may be performed to locate an information bearing point that is between sample points. Because the relative energy content of the signal is effectively independent of the specific information content, synchronization with the information bearing point is accomplished without requiring the insertion of any special information content or fixed content patterns into the signal.

Abstract: A system and method for information content-independent synchronization with a received signal. A variable of the signal (e.g., average energy or magnitude) which is related to the energy distribution, is measured over a period of time. The signal's information bearing point is found at the point within the information period of the signal with the highest averaged energy. The point may be found, for example, by detecting the sample point with highest average energy, or by correlating multiple sample points to a stored template. Interpolation may be performed to locate an information bearing point that is between sample points. Because the relative energy content of the signal is effectively independent of the specific information content, synchronization with the information bearing point is accomplished without requiring the insertion of any special information content or fixed content patterns into the signal.