Patents by Inventor Chia-Ming Yang
Chia-Ming Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250125216Abstract: The present disclosure provides a die. The die of the present disclosure has a top surface, a plurality of side surfaces, a bottom surface, a circuit layer and a platform. The bottom surface is connected to the side surfaces. The circuit layer is formed on the bottom surface. The platform is disposed around the top surface and is parallel to the top surface and the bottom surface. The distance from the platform to the bottom surface is less than that from the top surface to the bottom surface. The platform is perpendicularly connected to the side surfaces. The present disclosure further provides a method of manufacturing the above die and a semiconductor package with the die.Type: ApplicationFiled: October 4, 2024Publication date: April 17, 2025Inventors: YUEH-MING TUNG, CHIA-MING YANG, GUAN-LIN PAN, YING-CHIH LEE, PO-YEN YEN
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Publication number: 20250062265Abstract: The present disclosure provides a semiconductor package. The semiconductor package includes a heat spreader, a first die, a plurality of first conductive bumps, a molding layer and a redistribution layer. The first die is disposed on the heat spreader and has a top surface and a bottom surface opposing to the top surface. The first conductive bumps are disposed on the top surface of the first die and electrically connected to the first die. The molding layer is formed on the heat spreader to cover the top surface of the first die and expose the first conductive bumps. The redistribution layer is disposed on the molding layer to electrically connect to the first conductive bumps. The present disclosure further provides a method of manufacturing the above semiconductor package.Type: ApplicationFiled: March 15, 2024Publication date: February 20, 2025Inventors: YUEH-MING TUNG, Chia-Ming Yang, Tsun-Lung Hsieh, Ying-Chih Lee
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Publication number: 20250062281Abstract: The present disclosure provides a semiconductor package. The semiconductor package includes a first die, a plurality of first bonding pads, a plurality of first conductive bumps, a molding layer and a redistribution layer. The first die has a top surface and a bottom surface opposing to the top surface. The first bonding pads are disposed on the top surface of the first die. The first conductive bumps are disposed on the first bonding pads, and the first conductive bumps are electrically connected with the first die. The molding layer covers the top surface of the first die and exposes the first conductive bumps. The redistribution layer is disposed on the molding layer to electrically connect to the first conductive bumps. The present disclosure further provides a method of manufacturing the above semiconductor package.Type: ApplicationFiled: March 15, 2024Publication date: February 20, 2025Inventors: Yueh-Ming Tung, Chia-Ming Yang, Tsun-Lung Hsieh, Guan-Lin Pan, Po-Yen Yen
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Patent number: 11583848Abstract: The present invention discloses a nanoparticle control and detection system and operating method thereof. The present invention controls and detects the nanoparticles in the same device. The device comprises a first transparent electrode, a photoconductive layer, a spacer which is deposed on the edge of the photoconductive layer and a second transparent electrode. The aforementioned device controls and detects the nanoparticles by applying AC/DC bias and AC/DC light source to the transparent electrode.Type: GrantFiled: September 4, 2019Date of Patent: February 21, 2023Assignee: CHANG GUNG UNIVERSITYInventors: Chia-Ming Yang, Chao-Sung Lai, Yu-Ping Chen, Min-Hsien Wu
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Patent number: 11462454Abstract: The present disclosure provides a semiconductor package. The semiconductor package includes a redistribution layer, a die, a heat spreader, a thermal interface material and a molding layer. The die is disposed on the redistribution layer. The heat spreader is disposed on the die. The thermal interface material is applied between the heat spreader and the die. The molding layer is formed on the redistribution layer to enclose the die. The present disclosure further provides a method of manufacturing the above semiconductor package.Type: GrantFiled: January 26, 2021Date of Patent: October 4, 2022Assignee: ORIENT SEMICONDUCTOR ELECTRONICS, LIMITEDInventors: Yueh-Ming Tung, Chia-Ming Yang, Jung-Wei Chen, Jian-De Leu, Guan-Lin Pan
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Patent number: 11462485Abstract: The present disclosure provides an electronic package. The electronic package includes a substrate, an electronic component, a plurality of conductive elements, a metal sheet and a molding layer. The electronic component is disposed on the substrate and electrically connected to the substrate. The conductive elements are disposed on the substrate and electrically connected with the grounding circuit on the substrate. The metal sheet is disposed above the electronic component and is in electrical contact with the conductive elements. The molding layer is formed between the substrate and the metal sheet to enclose the electronic component and the conductive elements. The present disclosure further provides a method of manufacturing the above electronic package.Type: GrantFiled: March 23, 2021Date of Patent: October 4, 2022Assignee: ORIENT SEMICONDUCTOR ELECTRONICS, LIMITEDInventors: Yueh-Ming Tung, Chia-Ming Yang, Jung-Wei Chen, Ying-Chuan Li, Ping-Hua Chu
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Publication number: 20220285217Abstract: The wafer thinning method of the present disclosure includes: providing a wafer having a front surface and a back surface opposite to the front surface; grinding the back surface of the wafer with a grinding bit to thin the wafer to a predetermined thickness; dicing the wafer with a dicing blade; ablating the wafer by performing a chemical solution or plasma process on the back surface of the wafer to thin the wafer; and separating the wafer into a plurality of dies.Type: ApplicationFiled: March 29, 2021Publication date: September 8, 2022Inventors: YUEH-MING TUNG, CHIA-MING YANG, GUAN-LIN PAN, JUNG-WEI CHEN, JIAN-DE LEU
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Patent number: 11426793Abstract: A method is provided to fabricate a high-power module. A non-touching needle is used to paste a slurry on a heat-dissipation substrate. The slurry comprises nano-silver particles and micron silver particles. The ratio of the two silver particles is 9:1˜1:1. The slurry is pasted on the substrate to be heated up to a temperature kept holding. An integrated chip (IC) is put above the substrate to form a combined piece. A hot presser processes thermocompression to the combined piece to form a thermal-interface-material (TIM) layer with the IC and the substrate. After heat treatment, the TIM contains more than 99 percent of pure silver with only a small amount of organic matter. No volatile organic compounds would be generated after a long term of use. No intermetallic compounds would be generated while the stability under high temperature is obtained. Consequently, embrittlement owing to procedure temperature is dismissed.Type: GrantFiled: December 3, 2018Date of Patent: August 30, 2022Assignee: National Cheng Kung UniversityInventors: In-Gann Chen, Hung-Cheng Chen, Chia-Ming Yang, Steve Lien-Chung Hsu, Chang-Shu Kuo
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Publication number: 20220270981Abstract: The present disclosure provides an electronic package. The electronic package includes a substrate, an electronic component, a plurality of conductive elements, a metal sheet and a molding layer. The electronic component is disposed on the substrate and electrically connected to the substrate. The conductive elements are disposed on the substrate and electrically connected with the grounding circuit on the substrate. The metal sheet is disposed above the electronic component and is in electrical contact with the conductive elements. The molding layer is formed between the substrate and the metal sheet to enclose the electronic component and the conductive elements. The present disclosure further provides a method of manufacturing the above electronic package.Type: ApplicationFiled: March 23, 2021Publication date: August 25, 2022Inventors: YUEH-MING TUNG, CHIA-MING YANG, JUNG-WEI CHEN, YING-CHUAN LI, PING-HUA CHU
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Publication number: 20220199428Abstract: The method of manufacturing a semiconductor package of the present disclosure includes: providing a redistribution layer having opposing first surface and second surface; disposing a die on the first surface of the redistribution layer and electrically connecting the die to the redistribution layer; forming a mask on the second surface of the redistribution layer; performing a chemical or plasma etching process on the second surface of the redistribution layer to expose the conductive traces in the redistribution layer; removing the mask; and forming a plurality of conductive bumps on the second surface of the redistribution layer and electrically connecting the conductive bumps to the exposed conductive traces in the redistribution layer.Type: ApplicationFiled: February 2, 2021Publication date: June 23, 2022Inventors: YUEH-MING TUNG, CHIA-MING YANG, JUNG-WEI CHEN, JIAN-DE LEU, GUAN-LIN PAN
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Publication number: 20220189842Abstract: The present disclosure provides a semiconductor package. The semiconductor package includes a redistribution layer, a die, a heat spreader, a thermal interface material and a molding layer. The die is disposed on the redistribution layer. The heat spreader is disposed on the die. The thermal interface material is applied between the heat spreader and the die. The molding layer is formed on the redistribution layer to enclose the die. The present disclosure further provides a method of manufacturing the above semiconductor package.Type: ApplicationFiled: January 26, 2021Publication date: June 16, 2022Inventors: YUEH-MING TUNG, CHIA-MING YANG, JUNG-WEI CHEN, JIAN-DE LEU, GUAN-LIN PAN
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Patent number: 11355356Abstract: The method of manufacturing a semiconductor package of the present disclosure includes: providing a redistribution layer having opposing first surface and second surface; disposing a die on the first surface of the redistribution layer and electrically connecting the die to the redistribution layer; forming a mask on the second surface of the redistribution layer; performing a chemical or plasma etching process on the second surface of the redistribution layer to expose the conductive traces in the redistribution layer; removing the mask; and forming a plurality of conductive bumps on the second surface of the redistribution layer and electrically connecting the conductive bumps to the exposed conductive traces in the redistribution layer.Type: GrantFiled: February 2, 2021Date of Patent: June 7, 2022Assignee: ORIENT SEMICONDUCTOR ELECTRONICS, LIMITEDInventors: Yueh-Ming Tung, Chia-Ming Yang, Jung-Wei Chen, Jian-De Leu, Guan-Lin Pan
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Patent number: 11215399Abstract: A high temperature reaction system includes a reaction tube including a heating space, a discharge unit, a cooling unit, a feeding unit and an observation and analysis unit. The discharge unit is disposed opposite to an inlet of the heating space and has a discharge space communicating the heating space, and an observation window and a discharge opening which communicate the discharge space. The cooling unit has a cooling space communicating the discharge opening. The feeding unit includes a carrier holding a sample, and a moving module for moving the carrier and the sample. The observation and analysis unit includes an image capture module and an analysis module for analyzing gas released by the sample.Type: GrantFiled: December 6, 2019Date of Patent: January 4, 2022Assignee: National Cheng Kung UniversityInventors: In-Gann Chen, Shih-Hsien Liu, Ke-Miao Lu, Chia-Ming Yang, Hao-Hsun Chang
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Publication number: 20210170354Abstract: A high temperature reaction system includes a reaction tube including a heating space, a discharge unit, a cooling unit, a feeding unit and an observation and analysis unit. The discharge unit is disposed opposite to an inlet of the heating space and has a discharge space communicating the heating space, and an observation window and a discharge opening which communicate the discharge space. The cooling unit has a cooling space communicating the discharge opening. The feeding unit includes a carrier holding a sample, and a moving module for moving the carrier and the sample. The observation and analysis unit includes an image capture module and an analysis module for analyzing gas released by the sample.Type: ApplicationFiled: December 6, 2019Publication date: June 10, 2021Inventors: In-Gann CHEN, Shih-Hsien LIU, Ke-Miao LU, Chia-Ming YANG, Hao-Hsun CHANG
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Publication number: 20210016267Abstract: The present invention discloses a nanoparticle control and detection system and operating method thereof. The present invention controls and detects the nanoparticles in the same device. The device comprises a first transparent electrode, a photoconductive layer, a spacer which is deposed on the edge of the photoconductive layer and a second transparent electrode. The aforementioned device controls and detects the nanoparticles by applying AC/DC bias and AC/DC light source to the transparent electrode.Type: ApplicationFiled: September 4, 2019Publication date: January 21, 2021Inventors: CHIA-MING YANG, CHAO-SUNG LAI, YU-PING CHEN, MIN-HSIEN WU
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Publication number: 20210005574Abstract: The present disclosure provides a semiconductor package. The semiconductor package includes a first substrate, a first die, a plurality of first electrical contacts, a first encapsulant, a second substrate, a second die, a third die, a plurality of second electrical contacts, a second encapsulant and an adhesive layer. The first die is disposed on a first surface of the first substrate. The first electrical contacts are disposed on a second surface of the first substrate and are electrically connected to the first die. The first encapsulant is formed on the first surface of the first substrate to enclose the first die. The second and third dies are disposed on a first surface of the second substrate. The second electrical contacts are disposed on a second surface of the second substrate and are electrically connected to the second and third dies. The second encapsulant is formed on the first surface of the second substrate to enclose the second and third dies.Type: ApplicationFiled: March 11, 2020Publication date: January 7, 2021Inventors: YUEH-MING TUNG, CHIA-MING YANG, HUI-YEN TSAI, YU-CHEN LIN, PEI-JUNG SU
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Publication number: 20200371056Abstract: A gas sensing device comprises a silicon substrate, an insulating layer, a plasma treatment layer, a metal electrode and a sensing layer. The insulating layer is formed on the silicon substrate. The plasma treatment layer is formed on the insulating layer. The metal electrode is formed on the portion of the plasma treatment layer. The sensing layer is formed on a surface of the metal electrode and the plasma treatment layer. Through plasma treatment for the substrate and printing graphene film on the substrate and the electrode, the adsorption characteristics of gas selection ratio for graphene is improved, and the processing time of the plasma treatment is adjusted to optimize the sensing characteristics.Type: ApplicationFiled: September 9, 2019Publication date: November 26, 2020Inventors: CHAO-SUNG LAI, CHIA-MING YANG, TSUNG-CHENG CHEN, YU-CHENG YANG
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Patent number: 10685852Abstract: A chip packaging device is provided, which includes a main body unit, packaging unit and an aligning unit. The main body unit includes a mounting base, holder and a rotational platform. The packaging unit includes upper and lower bonding elements, upper and lower chips and a mask; a vertical axis is at the middle of the upper and the lower bonding elements, and a horizontal axis is above the lower bonding element. The aligning unit includes an aligning detector and a first focusing detector. When the lower chip and the mask are disposed on the lower bonding element, place the liquid sample in the mask and spread a packaging adhesive over the surface thereof; then, remove the mask and use the aligning detector and the first focusing detector to detect the position of the lower chip respectively, such that the chips can be aligned and bonded with each other.Type: GrantFiled: November 26, 2018Date of Patent: June 16, 2020Assignee: NATIONAL CHENG KUNG UNIVERSITYInventors: Po-Tsung Hsieh, Chia-Ming Yang, In-Gann Chen, Shih-Wen Tseng, Ya-Wen Tsai, Ya-Wen Chuang
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Publication number: 20200171578Abstract: A method is provided to fabricate a high-power module. A non-touching needle is used to paste a slurry on a heat-dissipation substrate. The slurry comprises nano-silver particles and micron silver particles. The ratio of the two silver particles is 9:1˜1:1. The slurry is pasted on the substrate to be heated up to a temperature kept holding. An integrated chip (IC) is put above the substrate to form a combined piece. A hot presser processes thermocompression to the combined piece to form a thermal-interface-material (TIM) layer with the IC and the substrate. After heat treatment, the TIM contains more than 99 percent of pure silver with only a small amount of organic matter. No volatile organic compounds would be generated after a long term of use. No intermetallic compounds would be generated while the stability under high temperature is obtained. Consequently, embrittlement owing to procedure temperature is dismissed.Type: ApplicationFiled: December 3, 2018Publication date: June 4, 2020Inventors: In-Gann Chen, Hung-Cheng Chen, Chia-Ming Yang, Steve Lien-Chung Hsu, Chang-Shu Kuo
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Patent number: 10663042Abstract: An external circulation ball screw consisting of a screw shaft, a screw nut, a cover, two reflow members and multiple rolling members is disclosed. The screw nut defines a mounting groove on the outer perimeter and two return holes in the mounting groove. A first half-return channel on a first step in the mounting groove of the screw nut and a second half-return channel in a second step inside the cover constitute a return channel. Alternatively, a third step can be formed in the cover, or the screw nut can be configured to provide a mounting groove and a third step with return holes in the mounting groove. Thus, same size of reflow members can be used with different lengths of return channels.Type: GrantFiled: July 2, 2018Date of Patent: May 26, 2020Assignee: HIWIN TECHNOLOGIES CORP.Inventors: Yi-Lung Sun, Chia-Ming Yang