Patents by Inventor Chian-Gauh Shih

Chian-Gauh Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Three-dimensional system-on-chip structure
    Patent number: 6593645
    Abstract: A three-dimensional system-on-chip structure comprises a plurality of chips and a plurality of plugs respectively fabricated in the chips. The chips are stacked on top of each other and each includes a periphery circuitry region. A plurality of contact pads is fabricated in each of the periphery circuitry regions. The plugs are formed in the corresponding stacked chips, and are electrically connected to the corresponding contact pads of two of the corresponding chips which are adjacent to each other, or two of the corresponding chips which are not adjacent to each other.
    Type: Grant
    Filed: March 1, 2001
    Date of Patent: July 15, 2003
    Assignee: United Microelectronics Corp.
    Inventors: Chian-Gauh Shih, Hsin-Pang Lu
  • Method of fabricating a three-dimensional system-on-chip and its structure
    Publication number: 20010006257
    Abstract: A three-dimensional system-on-chip structure comprises a plurality of chips and a plurality of plugs respectively fabricated in the chips. The chips are stacked on top of each other and each includes a periphery circuitry region. A plurality of contact pads is fabricated in each of the periphery circuitry regions. The plugs are formed in the corresponding stacked chips, and are electrically connected to the corresponding contact pads of two of the corresponding chips which are adjacent to each other, or two of the corresponding chips which are not adjacent to each other.
    Type: Application
    Filed: March 1, 2001
    Publication date: July 5, 2001
    Inventors: Chian-Gauh Shih, Hsin-Pang Lu
  • Power source design for embedded memory
    Patent number: 5970011
    Abstract: A power source design for embedded memory uses independent power sources such that a first power source group is linked to the DRAM, a second power source group is linked to the logic unit and a third power source group is linked to the testing mode circuit with input/output ports during the silicon chip stage. In the packaging stage the first power source group, the second power source group and the third power source group are joined together. The design is able to prevent testing errors or instability due to direct current from floating nodes in the silicon chip testing stage, and prevent a potential latch-up problem in the packaging stage.
    Type: Grant
    Filed: November 23, 1998
    Date of Patent: October 19, 1999
    Assignee: United Microelectronics Corp.
    Inventors: Chian-Gauh Shih, Cheng-Ju Hsieh, Jaris Yeh, Jacob Chen
  • Input and output circuit with wide voltage tolerance
    Patent number: 5969563
    Abstract: An input/output circuit with wide voltage tolerance is using a feedback circuit for increasing the voltage tolerance. A single gate oxide structure is fabricated instead of a dual gate oxide structure.
    Type: Grant
    Filed: June 17, 1998
    Date of Patent: October 19, 1999
    Assignee: United Microelectronics Corp.
    Inventors: Chian-Gauh Shih, Jiunn-Fu Liu, Yanan Mou