Patents by Inventor Chian-Min Ho

Chian-Min Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080066032
    Abstract: The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false answer cannot be provided e.g. when stopped due to resource constraints. In some embodiments, a measure of value N indicates that a given property that is being checked will not be violated within a distance N from an initial state from which the analysis started. Therefore, in such embodiments, a measure of value N indicates that the analysis has implicitly or explicitly covered every possible excursion of length N from the initial state, and formally proved that no counter-example is possible within this length N.
    Type: Application
    Filed: November 13, 2007
    Publication date: March 13, 2008
    Applicant: MENTOR GRAPHICS CORPORATION
    Inventors: Jeremy Levitt, Christophe Gauthron, Chian-Min Ho, Ping Yeung, Kalyana Mulam, Ramesh Sathianathan
  • Publication number: 20050131665
    Abstract: A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first-controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.
    Type: Application
    Filed: January 12, 2005
    Publication date: June 16, 2005
    Inventors: Chian-Min Ho, Robert Mardjuki, David Dill, Jing Lin, Ping Yeung, Paul Estrada, Jean-Charles Giomi, Tai Ly, Kalyana Mulam, Lawrence Widdoes, Paul Wilcox
  • Publication number: 20050081169
    Abstract: The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false answer cannot be provided e.g. when stopped due to resource constraints. In some embodiments, a measure of value N indicates that a given property that is being checked will not be violated within a distance N from an initial state from which the analysis started. Therefore, in such embodiments, a measure of value N indicates that the analysis has implicitly or explicitly covered every possible excursion of length N from the initial state, and formally proved that no counter-example is possible within this length N.
    Type: Application
    Filed: December 6, 2004
    Publication date: April 14, 2005
    Inventors: Jeremy Levitt, Christophe Gauthron, Chian-Min Ho, Ping Yeung, Kalyana Mulam, Ramesh Sathianathan