Patents by Inventor Chiang Cheng

Chiang Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11972072
    Abstract: The present disclosure provides an electronic device including a first sensing circuit, a second sensing circuit and a power line. The first sensing circuit includes a first sensing unit and a first transistor, and a first end of the first sensing unit is coupled to a control end of the first transistor. The second sensing circuit includes a second sensing unit and a second transistor, and a first end of the second sensing unit is coupled to a control end of the second transistor. A first end of the first transistor and a first end of the second transistor are coupled to the power line.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: April 30, 2024
    Assignee: InnoLux Corporation
    Inventors: Shu-Fen Li, Chuan-Chi Chien, Hsiao-Feng Liao, Rui-An Yu, Chang-Chiang Cheng, Po-Yang Chen, I-An Yao
  • Publication number: 20240113172
    Abstract: A semiconductor device includes a substrate, a channel layer, a gate structure, source/drain regions, and an insulating layer. The channel layer is disposed over the substrate. The gate structure is disposed over the channel layer. The source/drain regions are disposed over the substrate and disposed at two opposite sides of the channel layer. The insulating layer is disposed between the channel layer and the source/drain regions.
    Type: Application
    Filed: March 5, 2023
    Publication date: April 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Tse Hung, Meng-Zhan Li, Tzu-Chiang Chen, Chao-Ching Cheng, Iuliana Radu
  • Publication number: 20240105642
    Abstract: A method of manufacturing a package structure at least includes the following steps. An encapsulant laterally is formed to encapsulate the die and the plurality of through vias. A plurality of first connectors are formed to electrically connect to first surfaces of the plurality of through vias. A warpage control material is formed over the die, wherein the warpage control material is disposed to cover an entire surface of the die. A protection material is formed over the encapsulant and around the plurality of first connectors and the warpage control material. A coefficient of thermal expansion of the protection material is less than a coefficient of thermal expansion of the encapsulant.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Jan Pei, Ching-Hua Hsieh, Hsiu-Jen Lin, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Jen-Jui Yu, Cheng-Shiuan Wong
  • Publication number: 20240098125
    Abstract: The present disclosure relates to a system, a method and a computer-readable medium for rendering a streaming on a user terminal. The method includes rendering the streaming in a first mode, receiving an environment parameter of the user terminal, receiving a timing when the user terminal closes the streaming, determining a threshold value of the environment parameter based on the timing the user terminal closes the streaming, receiving an updated environment parameter of the user terminal, and rendering the streaming in a second mode if the updated environment parameter meets the threshold value. The second mode includes fewer data objects than the first mode or includes a downgraded version of a data object in the first mode for the rendering. The present disclosure can customize the rendering mode for each user and maximize the satisfaction of viewing streaming for each user.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Yung-Chi HSU, Chung-Chiang HSU, Shao-Yuan WU, Ming-Che CHENG, Ka Chon LOI
  • Publication number: 20240096757
    Abstract: An integrated circuit (IC) die includes first through third adjacent rows of through-silicon vias (TSVs), and first and second adjacent rows of memory macros. TSVs of the first row of TSVs extend through and are electrically isolated from memory macros of the first row of memory macros. TSVs of the third row of TSVs extend through and are electrically isolated from memory macros of the second row of memory macros.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Inventors: Hidehiro FUJIWARA, Tze-Chiang HUANG, Hong-Chen CHENG, Yen-Huei CHEN, Hung-Jen LIAO, Jonathan Tsung-Yung CHANG, Yun-Han LEE, Lee-Chung LU
  • Publication number: 20240088062
    Abstract: A package structure includes a die, an encapsulant laterally encapsulating the die, a warpage control material disposed over the die, and a protection material disposed over the encapsulant and around the warpage control material. A coefficient of thermal expansion of the protection material is less than a coefficient of thermal expansion of the encapsulant.
    Type: Application
    Filed: November 23, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Jan Pei, Ching-Hua Hsieh, Hsiu-Jen Lin, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Jen-Jui Yu, Cheng-Shiuan Wong
  • Patent number: 11929425
    Abstract: The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzu-Chung Wang, Chao-Ching Cheng, Tzu-Chiang Chen, Tung Ying Lee
  • Publication number: 20240079229
    Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes: forming a transistor region in a substrate; forming a gate dielectric layer over the transistor region; forming a diffusion-blocking layer over the gate dielectric layer; forming a first portion of a work function layer over the diffusion-blocking layer; forming a second portion of the work function layer over the first portion of the work function layer; forming a plurality of barrier elements on or under a top surface of the second portion of the work function layer; and forming a gate electrode over the work function layer, wherein the plurality of barrier elements block oxygen from diffusing into the work function layer during the formation of the gate electrode.
    Type: Application
    Filed: September 1, 2022
    Publication date: March 7, 2024
    Inventors: CHIA CHAN FAN, CHUNG-LIANG CHENG, CHIN-CHIA YEH, CHIEH CHIANG, CHENG YU PAI
  • Publication number: 20240061312
    Abstract: An electronic device including a first panel and a second panel overlapped with the first panel is provided. The first panel includes a substrate, a first medium layer, a first electrode layer and a second electrode layer. The first medium layer is disposed on the substrate. The first electrode layer is disposed between the substrate and the first medium layer. The second electrode layer is disposed between the first electrode layer and the first medium layer. A first voltage is applied to the first electrode layer, a second voltage is applied to the second electrode layer, and the first voltage is different from the second voltage.
    Type: Application
    Filed: August 18, 2022
    Publication date: February 22, 2024
    Applicant: Innolux Corporation
    Inventors: Mei-Wen Jao, Chang-Chiang Cheng, Yung-Hsun Wu, Rui-An Yu, Yi-Hsin Lin
  • Publication number: 20230314807
    Abstract: An electronic device includes a light modulation module. The light modulation module includes multiple first signal lines and multiple second signal lines. The first signal lines extend along a first direction. The second signal lines extend along a second direction. The second direction is different from the first direction. The first signal lines and the second signal lines are curves. Each of the first signal lines and each of the second signal lines respectively include multiple first patterns, and each of the first patterns has an inflection point.
    Type: Application
    Filed: February 8, 2023
    Publication date: October 5, 2023
    Applicant: Innolux Corporation
    Inventors: Huai-Ping Huang, Chih-Lung Lin, Chang-Chiang Cheng
  • Publication number: 20230314736
    Abstract: The present disclosure is generally directed to an optical transceiver housing for use in an optical transceiver module with at least one vapor chamber integrated into the transceiver housing. In more detail, the transceiver housing includes at least first and second housing portions on opposite sides and forming a compartment defined by one or more inner surfaces therein. The vapor chamber includes a heat input side and a heat output side on opposite sides of the vapor chamber. An outer wall of at least one of the housing portions may be defined at least in part by the heat output side of the vapor chamber such that the heat output side is exposed to outside of the transceiver housing for transferring heat from inside to outside the optical transceiver module.
    Type: Application
    Filed: April 4, 2022
    Publication date: October 5, 2023
    Inventors: Hao-Chiang CHENG, Kai-Sheng LIN, Kevin LIU
  • Publication number: 20230288449
    Abstract: The present invention provides a battery probing module, for testing a battery defined with a contact surface having a first electrode area and a second electrode area with different polarities. The battery probing module comprises a frame and a plurality of probe units. The frame has a top plate and a bottom plate opposite to the top plate. Each of the plurality of probe units comprises a base, a first probe, and a plurality of second probes. The base is defined with a top surface and a bottom surface deflectably fixed to the top surface by a fixing unit. The first probe and the plurality of second probes protrude from the bottom surface for contacting the first electrode area and the second electrode area respectively. Wherein the first probe is within a periphery surrounded by the plurality of second probes in a vertical direction of the bottom surface.
    Type: Application
    Filed: March 1, 2023
    Publication date: September 14, 2023
    Inventors: Shih-Ching TAN, Chun-Nan OU, Tzu-Fu CHEN, Chen-Chou WEN, Chiang-Cheng FAN
  • Patent number: 11698497
    Abstract: An optical fiber holder is disclosed herein that includes at least one confinement slot for routing intermediate optical fibers within a housing of an optical assembly module, and preferably, a plurality of confinement slots for maintaining a target/nominal fiber bending radius for one or more intermediate optical fibers within the housing. Preferably, the optical fiber holder is disposed within the housing of an optical subassembly between an optical component, e.g., a TOSA arrangement and/or ROSA arrangement, and optical coupling receptacles, e.g., LC coupling receptacles, for optically coupling with external fibers for sending and/or receiving optical signals.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: July 11, 2023
    Assignee: Applied Optoelectronics, Inc.
    Inventors: Hao-Chiang Cheng, Kai-Sheng Lin
  • Publication number: 20230188241
    Abstract: The present disclosure is generally directed to a holder that can be used to couple to and optically align an optical component with, for instance, an associated light path to launch or receive optical channel wavelengths along the same. The holder preferably includes a receptacle to couple to the optical component and a mounting section enables the holder to be securely coupled to a substrate in a manner that minimizes or otherwise reduces introducing component shift and resulting optical misalignment.
    Type: Application
    Filed: December 15, 2021
    Publication date: June 15, 2023
    Inventors: Kai-Sheng LIN, Hao-Chiang CHENG, Ziliang CAI
  • Publication number: 20230171533
    Abstract: A speaker is provided and includes a first speaker body, a second speaker body, a speaker component, and a sound transmission member. The first speaker body has a first chamber. The second speaker body has a second chamber. The second speaker body is received in the first chamber and defines a resonant cavity in the first chamber. The speaker component is disposed on the second speaker body and includes a supporting member, a magnet, a coil, and a diaphragm. Two ends of the supporting member are respectively inserted into the second chamber and fixed on the second speaker body. The magnet is disposed in the supporting member. The diaphragm is disposed on the supporting member and abuts against the second speaker body. The coil is received in the magnet and is connected to the diaphragm. The sound transmission member is coaxially disposed in the resonant cavity with the speaker component.
    Type: Application
    Filed: August 31, 2022
    Publication date: June 1, 2023
    Applicant: Lanto Electronic Limited
    Inventors: Kuan-Chun Liao, Chiao-Fan Huang, Chih-Chiang Cheng, You-Yu Lin, Hui-Yu Wang
  • Publication number: 20230168760
    Abstract: The present disclosure provides an electronic device including a first sensing circuit, a second sensing circuit and a power line. The first sensing circuit includes a first sensing unit and a first transistor, and a first end of the first sensing unit is coupled to a control end of the first transistor. The second sensing circuit includes a second sensing unit and a second transistor, and a first end of the second sensing unit is coupled to a control end of the second transistor. A first end of the first transistor and a first end of the second transistor are coupled to the power line.
    Type: Application
    Filed: November 1, 2022
    Publication date: June 1, 2023
    Applicant: InnoLux Corporation
    Inventors: Shu-Fen LI, Chuan-Chi CHIEN, Hsiao-Feng LIAO, Rui-An YU, Chang-Chiang CHENG, Po-Yang CHEN, I-An YAO
  • Publication number: 20230036433
    Abstract: An electronic device includes a substrate including an active area and a peripheral area adjacent to the active area; a plurality of spacers disposed in the active area and including a first spacer and a second spacer; a plurality of signal lines disposed on the substrate and extending along a first direction; a plurality of gate lines disposed on the substrate and extending along a second direction; and a gate driving unit disposed in the active area and including a receiving switch element and a buffer switch element, wherein the receiving switch element is disposed corresponding to the first spacer and receives an input signal through one of the signal lines, and the buffer switch element is disposed corresponding to the second spacer and is electrically connected to the receiving switch element, wherein the buffer switch element outputs a scan signal to one of the gate lines.
    Type: Application
    Filed: July 22, 2022
    Publication date: February 2, 2023
    Inventors: Huai-Ping HUANG, Rui-An YU, Chang-Chiang CHENG, Chia-Hao TSAI, Chih-Lung LIN, Jian-Min LEU
  • Patent number: 11532281
    Abstract: A display panel includes a first shift register, a first demultiplexer, a plurality of first gate lines, and a plurality of rows of first sub-pixels. The first shift register outputs a first shift signal. The first demultiplexer is coupled to the first shift register and receives the first shift signal and outputs a plurality of first gate driving signals. The plurality of first gate lines receive the plurality of first gate driving signals. Each row of first sub-pixels is coupled to a corresponding first gate line of the plurality of first gate lines. The first sub-pixels of the same row emit light of a same color.
    Type: Grant
    Filed: May 31, 2021
    Date of Patent: December 20, 2022
    Assignee: InnoLux Corporation
    Inventors: Yi-Shiuan Cherng, Chia-Hao Tsai, Chang-Chiang Cheng, Yung-Hsun Wu
  • Patent number: 11474311
    Abstract: A parabolic reflector device (also referred to herein as a parabolic lens device) is disclosed which includes a plurality of parabolic lens members and a mirror member which couple together and collectively provide a light-transmissive structure for multiplexing or demultiplexing of an optical signal. The parabolic reflector device can be implemented within optical subassembly modules to support operations of transmitter optical subassemblies (TOSAs) and/or receiver optical subassemblies (ROSAs).
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: October 18, 2022
    Assignee: Applied Optoelectronics, Inc.
    Inventors: Kai-Sheng Lin, Hao-Chiang Cheng, Ziliang Cai
  • Publication number: 20220283390
    Abstract: An optical fiber holder is disclosed herein that includes at least one confinement slot for routing intermediate optical fibers within a housing of an optical assembly module, and preferably, a plurality of confinement slots for maintaining a target/nominal fiber bending radius for one or more intermediate optical fibers within the housing. Preferably, the optical fiber holder is disposed within the housing of an optical subassembly between an optical component, e.g., a TOSA arrangement and/or ROSA arrangement, and optical coupling receptacles, e.g., LC coupling receptacles, for optically coupling with external fibers for sending and/or receiving optical signals.
    Type: Application
    Filed: March 4, 2021
    Publication date: September 8, 2022
    Inventors: Hao-Chiang CHENG, Kai-Sheng LIN