Patents by Inventor Chiang-Chung Tang
Chiang-Chung Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9215233Abstract: An identity authentication method is applied in a server which stores a relationship among a number of facial images, questions, and facial expressions. Each facial image corresponds to one or more questions. Each question corresponds to one facial expression. The method includes the following steps. Obtaining images captured with an electronic device when the electronic device attempts to login to the server. Determining whether the image comprises a human face matching one stored facial image. If yes, determining one or more questions corresponding to one facial image according to the relationship. Outputting the determined questions and then obtaining user images captured by the electronic device. Identifying the human face and a facial expression of the identified human face. Determining whether the identified facial expression matches the facial expression corresponding to the output question. If yes, determining that the identity authentication is successful.Type: GrantFiled: October 28, 2013Date of Patent: December 15, 2015Assignees: Patentcloud Corporation, Patentcloud Co. LimitedInventor: Chiang-Chung Tang
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Publication number: 20150095996Abstract: An identity authentication method is applied in a server which stores a relationship among a number of facial images, questions, and facial expressions. Each facial image corresponds to one or more questions. Each question corresponds to one facial expression. The method includes the following steps. Obtaining images captured with an electronic device when the electronic device attempts to login to the server. Determining whether the image comprises a human face matching one stored facial image. If yes, determining one or more questions corresponding to one facial image according to the relationship. Outputting the determined questions and then obtaining user images captured by the electronic device. Identifying the human face and a facial expression of the identified human face. Determining whether the identified facial expression matches the facial expression corresponding to the output question. If yes, determining that the identity authentication is successful.Type: ApplicationFiled: October 28, 2013Publication date: April 2, 2015Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventor: CHIANG-CHUNG TANG
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Patent number: 8838870Abstract: A baseboard management controller (BMC) connects with a COM serial port. The BMC includes an input queue and an output queue. If a basic input output system (BIOS) of the BMC has been initialized, the COM serial port is used by the BIOS. When a processor of the BMC sends a control command to a sharing system of the BMC, the input queue and the output queue are converted to time division multiplex (TDM) queues. The COM serial port may be used by the BIOS or by the BMC according to an ID flag of each element of the TDM queues.Type: GrantFiled: June 30, 2011Date of Patent: September 16, 2014Assignee: Hon Hai Precision Industry Co., Ltd.Inventor: Chiang-Chung Tang
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Patent number: 8549277Abstract: A server system includes a BMC, a BIOS chip, an IPMI and a diplexer. The BMC includes a first chip-selecting signal output terminal, a second chip-selecting signal output terminal, a first updating output terminal and a controlling input terminal. The BIOS chip includes a second chip-selecting signal input terminal and an updating input terminal. The IPMI has a controlling output terminal. The diplexer includes a first input terminal and an updating output terminal. The first input terminal of the diplexer is electrically coupled to the first updating output terminal of BMC. The updating output terminal of the diplexer is electrically coupled to the updating input terminal of the BIOS chip. The controlling output terminal of the IPMI is electrically coupled to the controlling input terminal of the BMC. The second chip-selecting signal input terminal of the BIOS chip is electrically coupled to the second chip-selecting signal output terminal of the BMC.Type: GrantFiled: September 17, 2010Date of Patent: October 1, 2013Assignee: Hon Hai Precision Industry Co., Ltd.Inventor: Chiang-Chung Tang
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Patent number: 8250264Abstract: A method for performing data backup using a storage device starts a backup battery when an electronic device is powered off, reads data from a memory of the electronic device by a system on chip (SoC) of the storage device, and writes the data into a field programmable gate array (FPGA) of the storage device. The method further encodes the data by the FPGA, and stores the encoded data into a flash memory of the storage device.Type: GrantFiled: December 18, 2009Date of Patent: August 21, 2012Assignee: Hon Hai Precision Industry Co., Ltd.Inventor: Chiang-Chung Tang
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Publication number: 20120144180Abstract: A baseboard management controller (BMC) connects with a COM serial port. The BMC includes an input queue and an output queue. If a basic input output system (BIOS) of the BMC has been initialized, the COM serial port is used by the BIOS. When a processor of the BMC sends a control command to a sharing system of the BMC, the input queue and the output queue are converted to time division multiplex (TDM) queues. The COM serial port may be used by the BIOS or by the BMC according to an ID flag of each element of the TDM queues.Type: ApplicationFiled: June 30, 2011Publication date: June 7, 2012Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventor: CHIANG-CHUNG TANG
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Publication number: 20120011355Abstract: A server system includes a BMC, a BIOS, an IPMI and a diplexer. The BMC includes a first chip-selecting signal output terminal, a second chip-selecting signal output terminal, a first updating output terminal and a controlling input terminal. The BIOS includes a second chip-selecting signal input terminal and an updating input terminal. The IPMI has a controlling output terminal. The diplexer includes a first input terminal and an updating output terminal. The first input terminal of the diplexer is electrically coupled to the first updating output terminal of BMC. The updating output terminal of the diplexer is electrically coupled to the updating input terminal of the BIOS. The controlling output terminal of the IPMI is electrically coupled to the controlling input terminal of the BMC. The second chip-selecting signal input terminal of the BIOS is electrically coupled to the second chip-selecting signal output terminal of the BMC.Type: ApplicationFiled: September 17, 2010Publication date: January 12, 2012Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventor: CHIANG-CHUNG TANG
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Patent number: 7971114Abstract: A method for testing a random-access memory (RAM) includes six tests. The first test is performed by performing a write and read test to storage locations of the RAM. The second test is performed by testing walking 1's across each data bus of the RAM. The third test is performed by testing walking 0's across the data bus of the RAM. The fourth test is performed by testing walking 1's across each address bus of the RAM. The fifth test is performed by testing walking 0's across the address bus bit of the RAM. The sixth test is performed by performing a write and read test to random blocks in the storage locations of the RAM.Type: GrantFiled: July 17, 2009Date of Patent: June 28, 2011Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.Inventors: Mo-Ying Tong, Xue-Wen Hong, Chiang-Chung Tang
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Patent number: 7971110Abstract: In a system and method for testing a serial attached small computer systems (SAS) interface of a SAS controller, the SAS controller connects to a loopback dongle via the SAS interface. The SAS interface sends a first data packet to the loopback dongle, and receives a second data packet from the loopback dongle. If information in the second data packet is the same as information in the first data packet, the system and method transmits a first notification indicating that the SAS interface is functioning normally. Otherwise, the system and method transmits a second notification indicating that the SAS interface is not functioning normally.Type: GrantFiled: September 25, 2009Date of Patent: June 28, 2011Assignee: Hon Hai Precision Industry Co., Ltd.Inventor: Chiang-Chung Tang
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Publication number: 20110029151Abstract: In a temperature adjustment system and method for a storage system, a corresponding relationship between data transfer rates of the storage system and rotational speeds of electric fans coupled to the storage system is established. Real-time data transfer rates of the storage system are measured. If there is a continuous increase or decrease in data transfer rates of the storage system, a rotational speed of the electric fans is determined according to the real-time data transfer rates and the corresponding relationship. The electric fans are controlled to run at the determined rotational speed.Type: ApplicationFiled: June 30, 2010Publication date: February 3, 2011Applicants: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD, HON HAI PRECISION INDUSTRY CO., LTD.Inventors: CHIANG-CHUNG TANG, WEI LIAO
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Publication number: 20110016262Abstract: A method for performing data backup using a storage device starts a backup battery when an electronic device is powered off, reads data from a memory of the electronic device by a system on chip (SoC) of the storage device, and writes the data into a field programmable gate array (FPGA) of the storage device. The method further encodes the data by the FPGA, and stores the encoded data into a flash memory of the storage device.Type: ApplicationFiled: December 18, 2009Publication date: January 20, 2011Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventor: CHIANG-CHUNG TANG
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Patent number: 7840843Abstract: A testing system for an embedded system is provided. The testing system includes a plurality of devices and one or more host computers. Each device, which includes the embedded system to be tested, is connected to the host computer via a network based on the network file system protocol. The host computers are further connected with a control server, and each of the host computers comprises a root file system. The control server is configured for providing an interface for a user to set test parameters, controlling each of the host computers to invoke a test program, thereby testing the embedded system according to the test parameters, and receiving test results of the embedded system from the host computer. A related testing method is also provided.Type: GrantFiled: August 25, 2008Date of Patent: November 23, 2010Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.Inventors: Mo-Ying Tong, Hua Dong, Xue-Wen Hong, Chiang-Chung Tang, Hong-Bo Zhao
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Publication number: 20100218043Abstract: In a system and method for testing a serial attached small computer systems (SAS) interface of a SAS controller, the SAS controller connects to a loopback dongle via the SAS interface. The SAS interface sends a first data packet to the loopback dongle, and receives a second data packet from the loopback dongle. If information in the second data packet is the same as information in the first data packet, the system and method transmits a first notification indicating that the SAS interface is functioning normally. Otherwise, the system and method transmits a second notification indicating that the SAS interface is not functioning normally.Type: ApplicationFiled: September 25, 2009Publication date: August 26, 2010Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventor: CHIANG-CHUNG TANG
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Publication number: 20100211835Abstract: A method for testing a random-access memory (RAM) includes six tests. The first test is performed by performing a write and read test to storage locations of the RAM. The second test is performed by testing walking 1's across each data bus of the RAM. The third test is performed by testing walking 0's across the data bus of the RAM. The fourth test is performed by testing walking 1's across each address bus of the RAM. The fifth test is performed by testing walking 0's across the address bus bit of the RAM. The sixth test is performed by performing a write and read test to random blocks in the storage locations of the RAM.Type: ApplicationFiled: July 17, 2009Publication date: August 19, 2010Applicants: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.Inventors: MO-YING TONG, XUE-WEN HONG, CHIANG-CHUNG TANG
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Publication number: 20090132857Abstract: A testing system for an embedded system is provided. The testing system includes a plurality of devices and one or more host computers. Each device, which includes the embedded system to be tested, is connected to the host computer via a network based on the network file system protocol. The host computers are further connected with a control server, and each of the host computers comprises a root file system. The control server is configured for providing an interface for a user to set test parameters, controlling each of the host computers to invoke a test program, thereby testing the embedded system according to the test parameters, and receiving test results of the embedded system from the host computer. A related testing method is also provided.Type: ApplicationFiled: August 25, 2008Publication date: May 21, 2009Applicants: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD, HON HAI PRECISION INDUSTRY CO., LTD.Inventors: MO-YING TONG, HUA DONG, XUE-WEN HONG, CHIANG-CHUNG TANG, HONG-BO ZHAO