Patents by Inventor Chiang-Hung Lin

Chiang-Hung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240427222
    Abstract: A crushable lens adapter ring includes a frame. The outer wall surface of one end of the frame has a first connecting portion for being connected to a first lens having a first diameter. The inner wall surface of the other end of the frame has a second connecting portion for being connected to a second lens having a second diameter. The frame has at least one force application portion and at least one crushable portion. At least a portion of the force application portion is adjacent to the crushable portion. When the force application portion is subjected to a force and displaced in a direction, the force application portion can force the frame to be broken and torn along the extension direction of the crushable portion.
    Type: Application
    Filed: May 28, 2024
    Publication date: December 26, 2024
    Inventor: Chiang-Hung Lin
  • Patent number: 9059142
    Abstract: A method for forming a semiconductor device with a vertical gate is disclosed, including providing a substrate, forming a recess in the substrate, forming a gate dielectric layer on a sidewall and a bottom of the recess, forming an adhesion layer in the recess and on the gate dielectric layer, wherein the adhesion layer is a metal silicide nitride layer, and forming a gate layer in the recess and on the adhesion layer.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: June 16, 2015
    Assignee: Nanya Technology Corporation
    Inventors: Wen-Ping Liang, Chiang-Hung Lin, Kuo-Hui Su
  • Patent number: 8815735
    Abstract: A semiconductor device comprises a substrate, a dielectric layer, an undoped silicon layer, and a silicon material. The substrate comprises a doped region. The dielectric layer is formed on the substrate and comprises a contact hole, and the contact hole corresponds to the doped region. The undoped silicon layer is formed on the doped region. The silicon material fills the contact hole from the undoped silicon layer.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: August 26, 2014
    Assignee: Nanya Technology Corporation
    Inventors: Yi Jung Chen, Kuo Hui Su, Chiang Hung Lin
  • Publication number: 20140021535
    Abstract: A method for forming a semiconductor device with a vertical gate is disclosed, including providing a substrate, forming a recess in the substrate, forming a gate dielectric layer on a sidewall and a bottom of the recess, forming an adhesion layer in the recess and on the gate dielectric layer, wherein the adhesion layer is a metal silicide nitride layer, and forming a gate layer in the recess and on the adhesion layer.
    Type: Application
    Filed: July 23, 2012
    Publication date: January 23, 2014
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Wen-Ping Liang, Chiang-Hung Lin, Kuo-Hui Su
  • Publication number: 20130292799
    Abstract: A semiconductor device comprises a substrate, a dielectric layer, an undoped silicon layer, and a silicon material. The substrate comprises a doped region. The dielectric layer is formed on the substrate and comprises a contact hole, and the contact hole corresponds to the doped region. The undoped silicon layer is formed on the doped region. The silicon material fills the contact hole from the undoped silicon layer.
    Type: Application
    Filed: May 3, 2012
    Publication date: November 7, 2013
    Inventors: Yi Jung CHEN, Kuo Hui Su, Chiang Hung Lin
  • Patent number: 8455984
    Abstract: A method of forming an integrated circuit structure comprises the steps of: providing a semiconductor substrate having a first side and a second side opposite the first side; forming a hole extending from the first side of the semiconductor substrate into the semiconductor substrate; filling the hole with conductive material; thinning the second side of the semiconductor substrate to a first predetermined thickness, so that the bottom of the hole does not protrude from the second side of the semiconductor substrate; and etching the second side of the semiconductor substrate to a second predetermined thickness, thereby exposing the bottom of the hole.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: June 4, 2013
    Assignee: Nanya Technology Corp.
    Inventors: Kee Wei Chung, Chiang Hung Lin, Neng Tai Shih
  • Publication number: 20130075812
    Abstract: A single-sided access device includes an active fin structure comprising a source contact area and a drain contact area separated from each other by an isolation region therebetween; a trench isolation structure disposed at one side of the active fin structure, wherein the trench isolation structure intersects with the isolation region between the source contact area and the drain contact area; a sidewall gate disposed under the isolation region and on the other side of the active fin structure opposite to the trench isolation structure so that the active fin structure is sandwiched by the trench isolation structure and the sidewall gate, wherein the sidewall gate has multi-fingers that engage with the active fin structure; and a gate dielectric layer between the sidewall gate and the active fin structure.
    Type: Application
    Filed: September 22, 2011
    Publication date: March 28, 2013
    Inventors: Hsin-Jung Ho, Jeng-Ping Lin, Neng-Tai Shih, Chang-Rong Wu, Chiang-Hung Lin, Chih-Huang Wu
  • Patent number: 8395209
    Abstract: A single-sided access device includes an active fin structure comprising a source contact area and a drain contact area separated from each other by an isolation region therebetween; a trench isolation structure disposed at one side of the active fin structure, wherein the trench isolation structure intersects with the isolation region between the source contact area and the drain contact area; a sidewall gate disposed under the isolation region and on the other side of the active fin structure opposite to the trench isolation structure so that the active fin structure is sandwiched by the trench isolation structure and the sidewall gate, wherein the sidewall gate has multi-fingers that engage with the active fin structure; and a gate dielectric layer between the sidewall gate and the active fin structure.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: March 12, 2013
    Assignee: Nanya Technology Corp.
    Inventors: Hsin-Jung Ho, Jeng-Ping Lin, Neng-Tai Shih, Chang-Rong Wu, Chiang-Hung Lin, Chih-Huang Wu
  • Publication number: 20120119355
    Abstract: A method of forming an integrated circuit structure comprises the steps of: providing a semiconductor substrate having a first side and a second side opposite the first side; forming a hole extending from the first side of the semiconductor substrate into the semiconductor substrate; filling the hole with conductive material; thinning the second side of the semiconductor substrate to a first predetermined thickness, so that the bottom of the hole does not protrude from the second side of the semiconductor substrate; and etching the second side of the semiconductor to substrate to a second predetermined thickness, thereby exposing the bottom of the hole.
    Type: Application
    Filed: November 15, 2010
    Publication date: May 17, 2012
    Applicant: NANYA TECHNOLOGY CORP.
    Inventors: KEE WEI CHUNG, CHIANG HUNG LIN, NENG TAI SHIH
  • Patent number: 8003528
    Abstract: A method for forming a semiconductor structure is provided. The method includes providing a substrate; forming a dielectric layer on the substrate; forming a conductor pattern on a main surface of the dielectric layer, the conductor pattern having a top surface and sidewalls; and performing a selective atomic layer deposition (ALD) process to selectively deposit a conformal metal layer onto the top surface and sidewalls of the conductor pattern, but without depositing onto the main surface of the dielectric layer substantially.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: August 23, 2011
    Assignee: Nanya Technology Corp.
    Inventors: Yi-Jen Lo, Yu-Shan Chiu, Kuo-Hui Su, Chiang-Hung Lin
  • Patent number: 7939421
    Abstract: A method for fabricating an integrated circuit structure includes the steps of forming a second dielectric layer on a substrate including a first conductive layer and a first dielectric layer, forming the second dielectric layer on the first conductive layer and the first dielectric layer, forming a hole exposing the first conductive layer in the second dielectric layer, forming a barrier layer inside the hole, and forming a second conductive layer on the barrier layer. In one embodiment of the present invention, the forming of the barrier layer comprises the steps of forming a metal layer in the hole, and performing a treating process in an atmosphere including a plasma formed from a gas including oxidant to form a metal oxide layer on the metal layer.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: May 10, 2011
    Assignee: Nanya Technology Corp.
    Inventor: Chiang Hung Lin
  • Publication number: 20110008961
    Abstract: A method for fabricating an integrated circuit structure includes the steps of forming a second dielectric layer on a substrate including a first conductive layer and a first dielectric layer, forming the second dielectric layer on the first conductive layer and the first dielectric layer, forming a hole exposing the first conductive layer in the second dielectric layer, forming a barrier layer inside the hole, and forming a second conductive layer on the barrier layer. In one embodiment of the present invention, the forming of the barrier layer comprises the steps of forming a metal layer in the hole, and performing a treating process in an atmosphere including a plasma formed from a gas including oxidant to form a metal oxide layer on the metal layer.
    Type: Application
    Filed: July 8, 2009
    Publication date: January 13, 2011
    Applicant: NANYA TECHNOLOGY CORP.
    Inventor: Chiang Hung Lin
  • Publication number: 20100276764
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate; a dielectric layer overlying the substrate; a conductor pattern on a main surface of the dielectric layer, the conductor pattern having a top surface and sidewalls; and a conformal metal layer selectively deposited on the top surface and sidewalls, but without deposited on the main surface of the dielectric layer substantially.
    Type: Application
    Filed: May 4, 2009
    Publication date: November 4, 2010
    Inventors: Yi-Jen Lo, Yu-Shan Chiu, Kuo-Hui Su, Chiang-Hung Lin
  • Publication number: 20100279498
    Abstract: A method for forming a semiconductor structure is provided. The method includes providing a substrate; forming a dielectric layer on the substrate; forming a conductor pattern on a main surface of the dielectric layer, the conductor pattern having a top surface and sidewalls; and performing a selective atomic layer deposition (ALD) process to selectively deposit a conformal metal layer onto the top surface and sidewalls of the conductor pattern, but without depositing onto the main surface of the dielectric layer substantially.
    Type: Application
    Filed: June 15, 2010
    Publication date: November 4, 2010
    Inventors: Yi-Jen Lo, Yu-Shan Chiu, Kuo-Hui Su, Chiang-Hung Lin
  • Patent number: 7341950
    Abstract: A method for controlling a thickness of a first layer of an electrical contact of a semiconductor device, whereby the semiconductor device comprises a semiconductor layer, a first layer and a second layer, whereby at least a part of the semi-conductor layer is covered with the first layer, whereby at least a part of the first layer is covered with the second layer, whereby the second layer is exposed to a plasma gas, whereby an upper face of the first layer adjacent to the second layer is treated by the plasma gas and an interlayer is generated between the first and the second layer reducing the thickness of the first layer.
    Type: Grant
    Filed: December 7, 2005
    Date of Patent: March 11, 2008
    Assignees: Infineon Technologies AG, Nanya Technology Corporation
    Inventors: Yi-Jen Lo, Axel Buerke, Sven Schmidbauer, Chiang-Hung Lin
  • Publication number: 20070125748
    Abstract: A method for controlling a thickness of a first layer of an electrical contact of a semiconductor device, whereby the semiconductor device comprises a semiconductor layer, a first layer and a second layer, whereby at least a part of the semi-conductor layer is covered with the first layer, whereby at least a part of the first layer is covered with the second layer, whereby the second layer is exposed to a plasma gas, whereby an upper face of the first layer adjacent to the second layer is treated by the plasma gas and an interlayer is generated between the first and the second layer reducing the thickness of the first layer.
    Type: Application
    Filed: December 7, 2005
    Publication date: June 7, 2007
    Applicants: INFINEON TECHNOLOGIES AG, NANYA TECHNOLOGY CORPORATION
    Inventors: Yi-Jen Lo, Axel Buerke, Sven Schmidbauer, Chiang-Hung Lin
  • Patent number: 6713745
    Abstract: The present invention provides a display device with feedback brightness sensing, suitable for using in a PDA, that comprises a LCD panel at an outside of which is installed a first photo-sensor for sensing a light brightness variation of its environment. A corresponding sensing signal is delivered to a first converter to be converted to a first digital reference signal that is delivered to a microprocessor for determining a brightness increase or decrease of the display panel. Via a light-guiding element and a second photo-sensor installed within the display panel, the light brightness from the display panel is sensed and converted to a second digital reference signal that is compared with the first digital reference signal to determine whether the display brightness is at an optimal value. An automatic brightness adjustment of the display device is thereby achieved to reduce power consumption and protect the user's eyes.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: March 30, 2004
    Assignee: Kinpo Electronics, Inc.
    Inventor: Chiang Hung Lin
  • Patent number: 6710318
    Abstract: A brightness feedback display device includes a LCD panel, a plurality of first photo-sensors for sensing the environmental brightness variation of the display device itself. Corresponding sensing signals are delivered to first converters for being converted to first digital reference signals that are delivered to a microprocessor, thereby determining how much brightness of the display panel increases or decreases. Via a light-guiding element and a second photo-sensor installed within the display panel, the light brightness from the display panel is sensed and converted to a second digital reference signal that is compared with the first digital reference signals to determine whether the display brightness is at an optimal value.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: March 23, 2004
    Assignee: Kinpo Electronics, Inc.
    Inventor: Chiang Hung Lin
  • Publication number: 20040017337
    Abstract: Adjustment device for light source of a panel, including a photosensitive resistor inlaid in the surface of the housing of a digital product for detecting the intensity of the light beam of ambient environment and changing the resistance. After the photosensitive resistor is serially connected with a resistor, via a voltage dividing point therebetween, the photosensitive resistor is connected to an A/D converter for detecting the variation of the resistance of the photosensitive resistor. The output of the A/D converter is connected to a CPU. The CPU controls a liquid crystal back light circuit to change the illumination of the back light or front light in accordance with the intensity of the light beam of ambient environment. Therefore, a power-saving effect and an eye-protective effect can be achieved.
    Type: Application
    Filed: July 24, 2002
    Publication date: January 29, 2004
    Applicant: Kinpo Electronics, Inc.
    Inventor: Chiang-Hung Lin
  • Publication number: 20040004608
    Abstract: A display device includes a display panel (LCD) applicable to a portable communication device such as a PDA or a web pad. The display device employs at least one photosensitive resistor for the purpose of sensing the variation of the environmental brightness, thereby adjusting the image brightness of the display panel.
    Type: Application
    Filed: July 3, 2002
    Publication date: January 8, 2004
    Applicant: Kinpo Electronics, Inc.
    Inventor: Chiang Hung Lin