Patents by Inventor Chiang-Hung Lin
Chiang-Hung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240427222Abstract: A crushable lens adapter ring includes a frame. The outer wall surface of one end of the frame has a first connecting portion for being connected to a first lens having a first diameter. The inner wall surface of the other end of the frame has a second connecting portion for being connected to a second lens having a second diameter. The frame has at least one force application portion and at least one crushable portion. At least a portion of the force application portion is adjacent to the crushable portion. When the force application portion is subjected to a force and displaced in a direction, the force application portion can force the frame to be broken and torn along the extension direction of the crushable portion.Type: ApplicationFiled: May 28, 2024Publication date: December 26, 2024Inventor: Chiang-Hung Lin
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Patent number: 9059142Abstract: A method for forming a semiconductor device with a vertical gate is disclosed, including providing a substrate, forming a recess in the substrate, forming a gate dielectric layer on a sidewall and a bottom of the recess, forming an adhesion layer in the recess and on the gate dielectric layer, wherein the adhesion layer is a metal silicide nitride layer, and forming a gate layer in the recess and on the adhesion layer.Type: GrantFiled: July 23, 2012Date of Patent: June 16, 2015Assignee: Nanya Technology CorporationInventors: Wen-Ping Liang, Chiang-Hung Lin, Kuo-Hui Su
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Patent number: 8815735Abstract: A semiconductor device comprises a substrate, a dielectric layer, an undoped silicon layer, and a silicon material. The substrate comprises a doped region. The dielectric layer is formed on the substrate and comprises a contact hole, and the contact hole corresponds to the doped region. The undoped silicon layer is formed on the doped region. The silicon material fills the contact hole from the undoped silicon layer.Type: GrantFiled: May 3, 2012Date of Patent: August 26, 2014Assignee: Nanya Technology CorporationInventors: Yi Jung Chen, Kuo Hui Su, Chiang Hung Lin
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Publication number: 20140021535Abstract: A method for forming a semiconductor device with a vertical gate is disclosed, including providing a substrate, forming a recess in the substrate, forming a gate dielectric layer on a sidewall and a bottom of the recess, forming an adhesion layer in the recess and on the gate dielectric layer, wherein the adhesion layer is a metal silicide nitride layer, and forming a gate layer in the recess and on the adhesion layer.Type: ApplicationFiled: July 23, 2012Publication date: January 23, 2014Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Wen-Ping Liang, Chiang-Hung Lin, Kuo-Hui Su
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Publication number: 20130292799Abstract: A semiconductor device comprises a substrate, a dielectric layer, an undoped silicon layer, and a silicon material. The substrate comprises a doped region. The dielectric layer is formed on the substrate and comprises a contact hole, and the contact hole corresponds to the doped region. The undoped silicon layer is formed on the doped region. The silicon material fills the contact hole from the undoped silicon layer.Type: ApplicationFiled: May 3, 2012Publication date: November 7, 2013Inventors: Yi Jung CHEN, Kuo Hui Su, Chiang Hung Lin
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Patent number: 8455984Abstract: A method of forming an integrated circuit structure comprises the steps of: providing a semiconductor substrate having a first side and a second side opposite the first side; forming a hole extending from the first side of the semiconductor substrate into the semiconductor substrate; filling the hole with conductive material; thinning the second side of the semiconductor substrate to a first predetermined thickness, so that the bottom of the hole does not protrude from the second side of the semiconductor substrate; and etching the second side of the semiconductor substrate to a second predetermined thickness, thereby exposing the bottom of the hole.Type: GrantFiled: November 15, 2010Date of Patent: June 4, 2013Assignee: Nanya Technology Corp.Inventors: Kee Wei Chung, Chiang Hung Lin, Neng Tai Shih
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Publication number: 20130075812Abstract: A single-sided access device includes an active fin structure comprising a source contact area and a drain contact area separated from each other by an isolation region therebetween; a trench isolation structure disposed at one side of the active fin structure, wherein the trench isolation structure intersects with the isolation region between the source contact area and the drain contact area; a sidewall gate disposed under the isolation region and on the other side of the active fin structure opposite to the trench isolation structure so that the active fin structure is sandwiched by the trench isolation structure and the sidewall gate, wherein the sidewall gate has multi-fingers that engage with the active fin structure; and a gate dielectric layer between the sidewall gate and the active fin structure.Type: ApplicationFiled: September 22, 2011Publication date: March 28, 2013Inventors: Hsin-Jung Ho, Jeng-Ping Lin, Neng-Tai Shih, Chang-Rong Wu, Chiang-Hung Lin, Chih-Huang Wu
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Patent number: 8395209Abstract: A single-sided access device includes an active fin structure comprising a source contact area and a drain contact area separated from each other by an isolation region therebetween; a trench isolation structure disposed at one side of the active fin structure, wherein the trench isolation structure intersects with the isolation region between the source contact area and the drain contact area; a sidewall gate disposed under the isolation region and on the other side of the active fin structure opposite to the trench isolation structure so that the active fin structure is sandwiched by the trench isolation structure and the sidewall gate, wherein the sidewall gate has multi-fingers that engage with the active fin structure; and a gate dielectric layer between the sidewall gate and the active fin structure.Type: GrantFiled: September 22, 2011Date of Patent: March 12, 2013Assignee: Nanya Technology Corp.Inventors: Hsin-Jung Ho, Jeng-Ping Lin, Neng-Tai Shih, Chang-Rong Wu, Chiang-Hung Lin, Chih-Huang Wu
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Publication number: 20120119355Abstract: A method of forming an integrated circuit structure comprises the steps of: providing a semiconductor substrate having a first side and a second side opposite the first side; forming a hole extending from the first side of the semiconductor substrate into the semiconductor substrate; filling the hole with conductive material; thinning the second side of the semiconductor substrate to a first predetermined thickness, so that the bottom of the hole does not protrude from the second side of the semiconductor substrate; and etching the second side of the semiconductor to substrate to a second predetermined thickness, thereby exposing the bottom of the hole.Type: ApplicationFiled: November 15, 2010Publication date: May 17, 2012Applicant: NANYA TECHNOLOGY CORP.Inventors: KEE WEI CHUNG, CHIANG HUNG LIN, NENG TAI SHIH
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Patent number: 8003528Abstract: A method for forming a semiconductor structure is provided. The method includes providing a substrate; forming a dielectric layer on the substrate; forming a conductor pattern on a main surface of the dielectric layer, the conductor pattern having a top surface and sidewalls; and performing a selective atomic layer deposition (ALD) process to selectively deposit a conformal metal layer onto the top surface and sidewalls of the conductor pattern, but without depositing onto the main surface of the dielectric layer substantially.Type: GrantFiled: June 15, 2010Date of Patent: August 23, 2011Assignee: Nanya Technology Corp.Inventors: Yi-Jen Lo, Yu-Shan Chiu, Kuo-Hui Su, Chiang-Hung Lin
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Patent number: 7939421Abstract: A method for fabricating an integrated circuit structure includes the steps of forming a second dielectric layer on a substrate including a first conductive layer and a first dielectric layer, forming the second dielectric layer on the first conductive layer and the first dielectric layer, forming a hole exposing the first conductive layer in the second dielectric layer, forming a barrier layer inside the hole, and forming a second conductive layer on the barrier layer. In one embodiment of the present invention, the forming of the barrier layer comprises the steps of forming a metal layer in the hole, and performing a treating process in an atmosphere including a plasma formed from a gas including oxidant to form a metal oxide layer on the metal layer.Type: GrantFiled: July 8, 2009Date of Patent: May 10, 2011Assignee: Nanya Technology Corp.Inventor: Chiang Hung Lin
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Publication number: 20110008961Abstract: A method for fabricating an integrated circuit structure includes the steps of forming a second dielectric layer on a substrate including a first conductive layer and a first dielectric layer, forming the second dielectric layer on the first conductive layer and the first dielectric layer, forming a hole exposing the first conductive layer in the second dielectric layer, forming a barrier layer inside the hole, and forming a second conductive layer on the barrier layer. In one embodiment of the present invention, the forming of the barrier layer comprises the steps of forming a metal layer in the hole, and performing a treating process in an atmosphere including a plasma formed from a gas including oxidant to form a metal oxide layer on the metal layer.Type: ApplicationFiled: July 8, 2009Publication date: January 13, 2011Applicant: NANYA TECHNOLOGY CORP.Inventor: Chiang Hung Lin
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Publication number: 20100276764Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate; a dielectric layer overlying the substrate; a conductor pattern on a main surface of the dielectric layer, the conductor pattern having a top surface and sidewalls; and a conformal metal layer selectively deposited on the top surface and sidewalls, but without deposited on the main surface of the dielectric layer substantially.Type: ApplicationFiled: May 4, 2009Publication date: November 4, 2010Inventors: Yi-Jen Lo, Yu-Shan Chiu, Kuo-Hui Su, Chiang-Hung Lin
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Publication number: 20100279498Abstract: A method for forming a semiconductor structure is provided. The method includes providing a substrate; forming a dielectric layer on the substrate; forming a conductor pattern on a main surface of the dielectric layer, the conductor pattern having a top surface and sidewalls; and performing a selective atomic layer deposition (ALD) process to selectively deposit a conformal metal layer onto the top surface and sidewalls of the conductor pattern, but without depositing onto the main surface of the dielectric layer substantially.Type: ApplicationFiled: June 15, 2010Publication date: November 4, 2010Inventors: Yi-Jen Lo, Yu-Shan Chiu, Kuo-Hui Su, Chiang-Hung Lin
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Patent number: 7341950Abstract: A method for controlling a thickness of a first layer of an electrical contact of a semiconductor device, whereby the semiconductor device comprises a semiconductor layer, a first layer and a second layer, whereby at least a part of the semi-conductor layer is covered with the first layer, whereby at least a part of the first layer is covered with the second layer, whereby the second layer is exposed to a plasma gas, whereby an upper face of the first layer adjacent to the second layer is treated by the plasma gas and an interlayer is generated between the first and the second layer reducing the thickness of the first layer.Type: GrantFiled: December 7, 2005Date of Patent: March 11, 2008Assignees: Infineon Technologies AG, Nanya Technology CorporationInventors: Yi-Jen Lo, Axel Buerke, Sven Schmidbauer, Chiang-Hung Lin
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Publication number: 20070125748Abstract: A method for controlling a thickness of a first layer of an electrical contact of a semiconductor device, whereby the semiconductor device comprises a semiconductor layer, a first layer and a second layer, whereby at least a part of the semi-conductor layer is covered with the first layer, whereby at least a part of the first layer is covered with the second layer, whereby the second layer is exposed to a plasma gas, whereby an upper face of the first layer adjacent to the second layer is treated by the plasma gas and an interlayer is generated between the first and the second layer reducing the thickness of the first layer.Type: ApplicationFiled: December 7, 2005Publication date: June 7, 2007Applicants: INFINEON TECHNOLOGIES AG, NANYA TECHNOLOGY CORPORATIONInventors: Yi-Jen Lo, Axel Buerke, Sven Schmidbauer, Chiang-Hung Lin
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Patent number: 6713745Abstract: The present invention provides a display device with feedback brightness sensing, suitable for using in a PDA, that comprises a LCD panel at an outside of which is installed a first photo-sensor for sensing a light brightness variation of its environment. A corresponding sensing signal is delivered to a first converter to be converted to a first digital reference signal that is delivered to a microprocessor for determining a brightness increase or decrease of the display panel. Via a light-guiding element and a second photo-sensor installed within the display panel, the light brightness from the display panel is sensed and converted to a second digital reference signal that is compared with the first digital reference signal to determine whether the display brightness is at an optimal value. An automatic brightness adjustment of the display device is thereby achieved to reduce power consumption and protect the user's eyes.Type: GrantFiled: June 28, 2002Date of Patent: March 30, 2004Assignee: Kinpo Electronics, Inc.Inventor: Chiang Hung Lin
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Patent number: 6710318Abstract: A brightness feedback display device includes a LCD panel, a plurality of first photo-sensors for sensing the environmental brightness variation of the display device itself. Corresponding sensing signals are delivered to first converters for being converted to first digital reference signals that are delivered to a microprocessor, thereby determining how much brightness of the display panel increases or decreases. Via a light-guiding element and a second photo-sensor installed within the display panel, the light brightness from the display panel is sensed and converted to a second digital reference signal that is compared with the first digital reference signals to determine whether the display brightness is at an optimal value.Type: GrantFiled: June 28, 2002Date of Patent: March 23, 2004Assignee: Kinpo Electronics, Inc.Inventor: Chiang Hung Lin
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Publication number: 20040017337Abstract: Adjustment device for light source of a panel, including a photosensitive resistor inlaid in the surface of the housing of a digital product for detecting the intensity of the light beam of ambient environment and changing the resistance. After the photosensitive resistor is serially connected with a resistor, via a voltage dividing point therebetween, the photosensitive resistor is connected to an A/D converter for detecting the variation of the resistance of the photosensitive resistor. The output of the A/D converter is connected to a CPU. The CPU controls a liquid crystal back light circuit to change the illumination of the back light or front light in accordance with the intensity of the light beam of ambient environment. Therefore, a power-saving effect and an eye-protective effect can be achieved.Type: ApplicationFiled: July 24, 2002Publication date: January 29, 2004Applicant: Kinpo Electronics, Inc.Inventor: Chiang-Hung Lin
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Publication number: 20040004608Abstract: A display device includes a display panel (LCD) applicable to a portable communication device such as a PDA or a web pad. The display device employs at least one photosensitive resistor for the purpose of sensing the variation of the environmental brightness, thereby adjusting the image brightness of the display panel.Type: ApplicationFiled: July 3, 2002Publication date: January 8, 2004Applicant: Kinpo Electronics, Inc.Inventor: Chiang Hung Lin