Patents by Inventor Chiang Liu

Chiang Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250146075
    Abstract: Among the various aspects of the present disclosure is the provision of methods of diagnosing and treating inflammatory bowel disease (IBD) including ulcerative colitis (UC) or Crohn's disease (CD). In particular, the present disclosure provides in part a panel of IBD biomarkers useful in diagnosing and making treatment decisions. In addition, the present disclosure provides methods of treating IBD with a plasminogen activator inhibitor-1 (PAI-1) inhibitor or tissue plasminogen activator (tPA).
    Type: Application
    Filed: January 9, 2025
    Publication date: May 8, 2025
    Inventors: Thaddeus STAPPENBECK, Gerard KAIKO, Ta-Chiang LIU
  • Patent number: 12271006
    Abstract: Disclosed is a cost-effective method to fabricate a multifunctional collimator structure for contact image sensors to filter ambient infrared light to reduce noises. In one embodiment, an optical collimator, includes: a dielectric layer; a substrate; a plurality of via holes; and a conductive layer, wherein the dielectric layer is formed over the substrate, wherein the plurality of via holes are configured as an array along a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of via holes extends through the dielectric layer and the substrate from the first surface of the dielectric layer to a second surface of the substrate in a vertical direction, and wherein the conductive layer is formed over at least one of the following: the first surface of the first dielectric layer and a portion of sidewalls of each of the plurality of via holes, and wherein the conductive layer is configured so as to allow the optical collimator to filter light in a range of wavelengths.
    Type: Grant
    Filed: August 8, 2023
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Yu Chen, Yen-Chiang Liu, Jiun-Jie Chiou, Jia-Syuan Li, You-Cheng Jhang, Shin-Hua Chen, Lavanya Sanagavarapu, Han-Zong Pan, Chun-Peng Li, Chia-Chun Hung, Ching-Hsiang Hu, Wei-Ding Wu, Jui-Chun Weng, Ji-Hong Chiang, Hsi-Cheng Hsu
  • Publication number: 20250087280
    Abstract: A method and a system for refreshing a flash memory device are provided. The system mainly includes a host, and a main control unit and a plurality of flash memory units arranged in the flash memory device. The method includes the following steps: providing a performance value of the plurality of flash memory units from the main control unit to the host; providing a refresh command from the host to the main control unit when the performance value is lower than a pre-determined value; and controling the plurality of flash memory units, by the the main control unit, to stop current operations, and executing a refresh operation on the plurality of flash memory units.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 13, 2025
    Applicant: INNODISK CORPORATION
    Inventors: Ting-Chiang Liu, Chung-Yi Lai
  • Publication number: 20250054817
    Abstract: In a method of fabricating at least one IC, doped regions are formed on a semiconductor wafer using a first photolithography mask, including at least one doped region of a test structure. Active regions are formed on the semiconductor wafer using a second photolithography mask, including active regions of the test structure. Electrical contacts are formed on the active regions of the test structure. Electrical resistances are measured between pairs of active regions of the test structure using the electrical contacts. At least one metric is determined indicating whether the doped regions are spatially aligned with the active regions based on the measured electrical resistances. In response to the at least one metric indicating the doped regions are spatially aligned with the active regions, completing fabrication of the at least one integrated circuit.
    Type: Application
    Filed: August 7, 2023
    Publication date: February 13, 2025
    Inventors: Wei-Kuan Yen, Yi-Cheng Chiu, Yen-Chiang Liu, Kang-Tai Peng, Jui-Chun Weng
  • Publication number: 20240361609
    Abstract: Disclosed is a method to fabricate a multifunctional collimator structure In one embodiment, an optical collimator, includes: a dielectric layer; a substrate; and a plurality of via holes, wherein the dielectric layer is formed over the substrate, wherein the plurality of via holes are configured as an array along a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of via holes extends through the dielectric layer and the substrate from the first surface of the dielectric layer to a second surface of the substrate in a vertical direction, wherein the substrate has a bulk impurity doping concentration equal to or greater than 1×1019 per cubic centimeter (cm?3) and a first thickness, and wherein the bulk impurity doping concentration and the first thickness of the substrate are configured so as to allow the optical collimator to filter light in a range of wavelengths.
    Type: Application
    Filed: July 11, 2024
    Publication date: October 31, 2024
    Inventors: Hsin-Yu CHEN, Chun-Peng LI, Chia-Chun HUNG, Ching-Hsiang HU, Wei-Ding WU, Jui-Chun WENG, Ji-Hong CHIANG, Yen Chiang LIU, Jiun-Jie CHIOU, Li-Yang TU, Jia-Syuan LI, You-Cheng JHANG, Shin-Hua CHEN, Lavanya SANAGAVARAPU, Han-Zong PAN, Hsi-Cheng HSU
  • Patent number: 12092839
    Abstract: Disclosed is a method to fabricate a multifunctional collimator structure In one embodiment, an optical collimator, includes: a dielectric layer; a substrate; and a plurality of via holes, wherein the dielectric layer is formed over the substrate, wherein the plurality of via holes are configured as an array along a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of via holes extends through the dielectric layer and the substrate from the first surface of the dielectric layer to a second surface of the substrate in a vertical direction, wherein the substrate has a bulk impurity doping concentration equal to or greater than 1×1019 per cubic centimeter (cm?3) and a first thickness, and wherein the bulk impurity doping concentration and the first thickness of the substrate are configured so as to allow the optical collimator to filter light in a range of wavelengths.
    Type: Grant
    Filed: July 14, 2023
    Date of Patent: September 17, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Yu Chen, Chun-Peng Li, Chia-Chun Hung, Ching-Hsiang Hu, Wei-Ding Wu, Jui-Chun Weng, Ji-Hong Chiang, Yen Chiang Liu, Jiun-Jie Chiou, Li-Yang Tu, Jia-Syuan Li, You-Cheng Jhang, Shin-Hua Chen, Lavanya Sanagavarapu, Han-Zong Pan, Hsi-Cheng Hsu
  • Patent number: 11922027
    Abstract: A memory access speed adjustment method, control device and memory module are provided. The method is for use in controlling a controller of a memory and includes steps of: obtaining a current temperature value of the memory; determining an access speed threshold of the memory according to a continuous variation relation with respect to a difference between the current temperature value and a target temperature value; and adjusting, by the controller, an access speed of the memory according to the access speed threshold.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: March 5, 2024
    Assignee: INNODISK CORPORATION
    Inventors: Chung-Ting Huang, Chung-Yi Lai, Ting-Chiang Liu
  • Patent number: 11915969
    Abstract: A semiconductor structure including a substrate and a deep trench isolation structure is provided. The deep trench isolation structure is disposed in the substrate and is not electrically connected to any device. The deep trench isolation structure includes a heat dissipation layer and a dielectric liner layer. The heat dissipation layer is disposed in the substrate. The dielectric liner layer is disposed between the heat dissipation layer and the substrate.
    Type: Grant
    Filed: March 6, 2022
    Date of Patent: February 27, 2024
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chen-Chiang Liu, Hung-Kwei Liao
  • Patent number: 11890519
    Abstract: A method and an apparatus for impact position detection of impact sport equipment are provided. The method includes following steps: retrieving a vibration signal generated by a vibration sensor detecting vibration caused by impact of impact sport equipment and a ball; performing a spectrum analysis on the vibration signal to obtain eigenfrequencies of the vibration signal in a frequency domain; and calculating at least one piece of characteristic information by using an amplitude of each eigenfrequency and inputting the same into a prediction model established in advance by using machine learning, so as to estimate an impact position of the ball on the impact sport equipment, in which the prediction model is trained by using characteristic information of multiple vibration signals and corresponding impact positions.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: February 6, 2024
    Assignee: National Tsing Hua University
    Inventors: Yang Chih Feng, Chiang Liu, Hsi-Pin Ma
  • Patent number: 11867701
    Abstract: The present disclosure provides methods for classifying a cell as abnormal based on HD5 protein detection as well as methods for predicting prognosis of a subject with Crohn's disease based on HD5 protein detection.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: January 9, 2024
    Assignee: Washington University
    Inventors: Thaddeus Stappenbeck, Ta-Chiang Liu, Kelli VanDussen
  • Publication number: 20230400699
    Abstract: Disclosed is a cost-effective method to fabricate a multifunctional collimator structure for contact image sensors to filter ambient infrared light to reduce noises. In one embodiment, an optical collimator, includes: a dielectric layer; a substrate; a plurality of via holes; and a conductive layer, wherein the dielectric layer is formed over the substrate, wherein the plurality of via holes are configured as an array along a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of via holes extends through the dielectric layer and the substrate from the first surface of the dielectric layer to a second surface of the substrate in a vertical direction, and wherein the conductive layer is formed over at least one of the following: the first surface of the first dielectric layer and a portion of sidewalls of each of the plurality of via holes, and wherein the conductive layer is configured so as to allow the optical collimator to filter light in a range of wavelengths.
    Type: Application
    Filed: August 8, 2023
    Publication date: December 14, 2023
    Inventors: Hsin-Yu CHEN, Yen-Chiang LIU, June-Jie CHIOU, Jia-Syuan LI, You-Cheng JHANG, Shin-Hua CHEN, LAVANYA SANAGAVARAPU, Han-Zong PAN, Chun-Peng LI, Chia-Chun HUNG, Ching-Hsiang HU, Wei-Ding WU, Jui-Chun WENG, Ji-Hong CHIANG, Hsi-Cheng HSU
  • Publication number: 20230359056
    Abstract: Disclosed is a method to fabricate a multifunctional collimator structure In one embodiment, an optical collimator, includes: a dielectric layer; a substrate; and a plurality of via holes, wherein the dielectric layer is formed over the substrate, wherein the plurality of via holes are configured as an array along a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of via holes extends through the dielectric layer and the substrate from the first surface of the dielectric layer to a second surface of the substrate in a vertical direction, wherein the substrate has a bulk impurity doping concentration equal to or greater than 1×1019 per cubic centimeter (cm?3) and a first thickness, and wherein the bulk impurity doping concentration and the first thickness of the substrate are configured so as to allow the optical collimator to filter light in a range of wavelengths.
    Type: Application
    Filed: July 14, 2023
    Publication date: November 9, 2023
    Inventors: Hsin-Yu CHEN, Chun-Peng LI, Chia-Chun HUNG, Ching-Hsiang HU, Wei-Ding WU, Jui-Chun WENG, JI-Hong CHIANG, Yen-Chiang LIU, Jiun-Jie CHIOU, Li-Yang TU, Jia-Syuan LI, You-Cheng JHANG, Shin-Hua CHEN, Lavanya SANAGAVARAPU, Han-Zong PAN, Hsi-Cheng HSU
  • Patent number: 11782284
    Abstract: Disclosed is a cost-effective method to fabricate a multifunctional collimator structure for contact image sensors to filter ambient infrared light to reduce noises. In one embodiment, an optical collimator, includes: a dielectric layer; a substrate; a plurality of via holes; and a conductive layer, wherein the dielectric layer is formed over the substrate, wherein the plurality of via holes are configured as an array along a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of via holes extends through the dielectric layer and the substrate from the first surface of the dielectric layer to a second surface of the substrate in a vertical direction.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: October 10, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Yu Chen, Yen-Chiang Liu, Jiun-Jie Chiou, Jia-Syuan Li, You-Cheng Jhang, Shin-Hua Chen, Lavanya Sanagavarapu, Han-Zong Pan, Chun-Peng Li, Chia-Chun Hung, Ching-Hsiang Hu, Wei-Ding Wu, Jui-Chun Weng, Ji-Hong Chiang, Hsi-Cheng Hsu
  • Publication number: 20230313305
    Abstract: Among the various aspects of the present disclosure is the provision of methods of diagnosing and treating inflammatory bowel disease (IBD) including ulcerative colitis (UC) or Crohn's disease (CD). In particular, the present disclosure provides in part a panel of IBD biomarkers useful in diagnosing and making treatment decisions. In addition, the present disclosure provides methods of treating IBD with a plasminogen activator inhibitor-1(PAI-1) inhibitor or tissue plasminogen activator (tPA).
    Type: Application
    Filed: March 16, 2023
    Publication date: October 5, 2023
    Inventors: Thaddeus Stappenbeck, Gerard Kaiko, Ta-Chiang Liu
  • Patent number: 11747395
    Abstract: A board-like connector, a single-arm bridge of a board-like connector, and a wafer testing assembly are provided. The board-like connector includes a plurality of single-arm bridges spaced apart from each other and an insulating layer. Each of the single-arm bridges includes a carrier, a cantilever extending from and being coplanar with the carrier, an abutting column, and an abutting end portion, the latter two of which extend from the cantilever and are respectively arranged at two opposite sides of the cantilever. The insulating layer connects the carriers of the single-arm bridges, and the abutting column of each of the single-arm bridges protrudes from the insulating layer. The abutting column and the abutting end portion of each of the single-arm bridges are configured to abut against two boards, respectively.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: September 5, 2023
    Assignee: CHUNGHWA PRECISION TEST TECH. CO., LTD.
    Inventors: Kai-Chieh Hsieh, Chao-Chiang Liu, Meng-Chieh Cheng, Wei-Jhih Su
  • Publication number: 20230256311
    Abstract: A method and an apparatus for impact position detection of impact sport equipment are provided. The method includes following steps: retrieving a vibration signal generated by a vibration sensor detecting vibration caused by impact of impact sport equipment and a ball; performing a spectrum analysis on the vibration signal to obtain eigenfrequencies of the vibration signal in a frequency domain; and calculating at least one piece of characteristic information by using an amplitude of each eigenfrequency and inputting the same into a prediction model established in advance by using machine learning, so as to estimate an impact position of the ball on the impact sport equipment, in which the prediction model is trained by using characteristic information of multiple vibration signals and corresponding impact positions.
    Type: Application
    Filed: April 11, 2022
    Publication date: August 17, 2023
    Applicant: National Tsing Hua University
    Inventors: Yang Chih Feng, Chiang Liu, Hsi-Pin Ma
  • Patent number: 11726342
    Abstract: Disclosed is a method to fabricate a multifunctional collimator structure In one embodiment, an optical collimator, includes: a dielectric layer; a substrate; and a plurality of via holes, wherein the dielectric layer is formed over the substrate, wherein the plurality of via holes are configured as an array along a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of via holes extends through the dielectric layer and the substrate from the first surface of the dielectric layer to a second surface of the substrate in a vertical direction, wherein the substrate has a bulk impurity doping concentration equal to or greater than 1×1019 per cubic centimeter (cm?3) and a first thickness, and wherein the bulk impurity doping concentration and the first thickness of the substrate are configured so as to allow the optical collimator to filter light in a range of wavelengths.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: August 15, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Yu Chen, Chun-Peng Li, Chia-Chun Hung, Ching-Hsiang Hu, Wei-Ding Wu, Jui-Chun Weng, Ji-Hong Chiang, Yen Chiang Liu, Jiun-Jie Chiou, Li-Yang Tu, Jia-Syuan Li, You-Cheng Jhang, Shin-Hua Chen, Lavanya Sanagavarapu, Han-Zong Pan, Hsi-Cheng Hsu
  • Publication number: 20230238270
    Abstract: A semiconductor structure including a substrate and a deep trench isolation structure is provided. The deep trench isolation structure is disposed in the substrate and is not electrically connected to any device. The deep trench isolation structure includes a heat dissipation layer and a dielectric liner layer. The heat dissipation layer is disposed in the substrate. The dielectric liner layer is disposed between the heat dissipation layer and the substrate.
    Type: Application
    Filed: March 6, 2022
    Publication date: July 27, 2023
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chen-Chiang Liu, Hung-Kwei Liao
  • Publication number: 20230236738
    Abstract: A memory access speed adjustment method, control device and memory module are provided. The method is for use in controlling a controller of a memory and includes steps of: obtaining a current temperature value of the memory; determining an access speed threshold of the memory according to a continuous variation relation with respect to a difference between the current temperature value and a target temperature value; and adjusting, by the controller, an access speed of the memory according to the access speed threshold.
    Type: Application
    Filed: April 8, 2022
    Publication date: July 27, 2023
    Inventors: CHUNG-TING HUANG, CHUNG-YI LAI, TING-CHIANG LIU
  • Patent number: 11699871
    Abstract: A board-like connector, a dual-arm bridge of a board-like connector, and a wafer testing assembly are provided. The board-like connector includes a plurality of dual-arm bridges spaced apart from each other and an insulating layer. Each of the dual-arm bridges includes a carrier, a first cantilever, a second cantilever, a first abutting column, and a second abutting column, the latter two of which extend from the first and second cantilevers along two opposite directions. The first cantilever and the second cantilever extend from and are coplanar with the carrier. The insulating layer connects the carriers of the dual-arm bridges. The first abutting column and second abutting column of each of the dual-arm bridges respectively protrude from two opposite sides of the insulating layer, and are configured to abut against two boards, respectively.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: July 11, 2023
    Assignee: CHUNGHWA PRECISION TEST TECH. CO., LTD.
    Inventors: Kai-Chieh Hsieh, Chao-Chiang Liu, Meng-Chieh Cheng, Wei-Jhih Su