Patents by Inventor Chiang Wu

Chiang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250253776
    Abstract: A bidirectional voltage conversion device includes a first half-bridge switching circuit, a transformer, a first resonant capacitor, a double-pole double-throw relay, a second half-bridge switching circuit, a resonant inductor and a second resonant capacitor. The first half-bridge switching circuit is coupled to a high-voltage power storage device. The first resonant capacitor is coupled to the first half-bridge switching circuit and a primary winding. The double-pole double-throw relay is coupled to a first secondary winding, a second secondary winding and a grounding terminal. The second half-bridge switching circuit is coupled to a low-voltage power storage device. The resonant inductor and the second resonant capacitor are coupled in series between the second half-bridge switching circuit and a node between the first secondary winding and the second secondary winding.
    Type: Application
    Filed: July 9, 2024
    Publication date: August 7, 2025
    Applicant: National Yang Ming Chiao Tung University
    Inventors: Wei-Hua CHIENG, Edward Yi CHANG, Stone CHENG, Ching-Yao LIU, Yueh-Tsung SHIEH, Li-Chuan TANG, Chih-Chiang WU, Wen-Yuh SHIEH, Chi-Chun HUANG, Gang-Ting LIOU
  • Publication number: 20250244546
    Abstract: An optical system includes a flexible transmission member and a laser emitting module. The flexible transmission member is a single one-piece structure and includes a first light channel, a second light channel, a third light channel, and a light-combining channel. The second light channel is arranged between the first light channel and the third light channel. The shapes and widths of the first light channel, the second light channel, and the third light channel are different from each other, and the light-combining channel is connected to the first light channel, the second light channel, and the third light channel. The laser emitting module can emit a red light beam, a green light beam, and a blue light beam, which respectively travel in the first light channel, the second light channel, and the third light channel for being combined into a white light beam in the light-combining channel.
    Type: Application
    Filed: September 6, 2024
    Publication date: July 31, 2025
    Inventors: CHIH-HAN YEN, HAN-CHIANG WU, TING-QING CHEN, YU-YI CHIEN
  • Patent number: 12376395
    Abstract: An optical device is provided. The optical device includes a substrate and a plurality of optical structures. The substrate includes a plurality of photoelectric conversion elements. The optical structures are disposed above the substrate. Each optical structure corresponds to one photoelectric conversion element. Each optical structure includes a first portion and a second portion. The first portion has a first glass transition temperature. The second portion has a second glass transition temperature. The second portion guides the incident light into the photoelectric conversion element. The first glass transition temperature is higher than the second glass transition temperature.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: July 29, 2025
    Assignee: VISERA TECHNOLOGIES COMPANY LIMITED
    Inventors: Shin-Hong Kuo, Han-Lin Wu, Ta-Yung Ni, Ching-Chiang Wu, Zong-Ru Tu, Yu-Chi Chang, Hung-Jen Tsai
  • Publication number: 20250240985
    Abstract: The invention provides a semiconductor structure with a deep trench capacitor structures, which comprises a substrate, the substrate comprises a bottle-shaped trench, wherein the bottle-shaped trench has an upper part and a lower part in a cross section, and the interface between the upper part and the lower part is a bottleneck line, wherein the bottleneck line is the part with the smallest width in the bottle-shaped trench, a first dielectric layer is filled in the bottle-shaped trench, and a void is located in the first dielectric layer, wherein the highest point of the void is lower than the bottleneck line.
    Type: Application
    Filed: February 21, 2024
    Publication date: July 24, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Fan Li, Nan-Yuan Huang, Kuan-Jhih Hou, Yu-Fu Wang, Ya-Yin Hsiao, Po-Ching Su, Ti-Bin Chen, Chih-Chiang Wu, Yao-Jhan Wang
  • Patent number: 12369315
    Abstract: A semiconductor structure and a method making it are disclosed. The method includes: providing a substrate, and sequentially forming a bitline contact structure and a bitline on the substrate; the bitline includes a connection layer connected to the bitline contact structure. The bitline contact structure and the sidewalls of the connection layer are etched back. A first silicide layer covering the sidewalls of the bitline contact structure, and a second silicide layer covering the sidewalls of the connection layer are formed. This structure can reduce the contact resistance between the bitline contact structure and the bitline, as well as the parasitic capacitance between the bitline contact structure and the adjacent conductive structures, thereby improving the electrical performance and reliability of the semiconductor structure and improving the semiconductor yield.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: July 22, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Tieh-Chiang Wu, Lingxin Zhu
  • Publication number: 20250232399
    Abstract: This disclosure provides a demosaicing device and a demosaicing method for image sensor. The method includes capturing a panchromatic image by using a pixel array including switchable pixels and clear pixels, where the panchromatic image is captured when the switchable pixels and the clear pixels are under a clear state. The method includes capturing a chromic image by using the pixel array when the switchable pixels are under a color state and the clear pixels are under the clear state. The method includes performing a weighted average calculation and a signal subtraction on the chromic image and the panchromatic image to generate first resolution chromic images. A resolution of the first resolution chromic images is the same as a resolution of the panchromatic image and the chromic image. The method includes fusing the first resolution chromic images with the panchromatic image to generate demosaiced chromic images.
    Type: Application
    Filed: January 12, 2024
    Publication date: July 17, 2025
    Inventors: Wei-Lung TSAI, Ching-Chiang WU
  • Patent number: 12356656
    Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.
    Type: Grant
    Filed: May 21, 2024
    Date of Patent: July 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Chia-Ching Lee, Chung-Chiang Wu, Ching-Hwanq Su
  • Publication number: 20250212426
    Abstract: A MIM capacitor structure includes a semiconductor substrate, and a first trench and a second trench in the semiconductor substrate in a capacitance forming region. The second trench is adjacent to the first trench. The second trench is deeper than the first trench. A dielectric liner layer conformally covers a top surface of the semiconductor substrate and interior surfaces of the first trench and the second trench. A bottom electrode layer conformally covers the dielectric liner layer. The bottom electrode layer extends onto a top surface of the semiconductor substrate. A capacitor dielectric layer is disposed on the bottom electrode layer in the first trench and the second trench. A top electrode layer is disposed on the capacitor dielectric layer in the first trench and the second trench. The top surface of the top electrode layer is coplanar with the top surface of the bottom electrode layer.
    Type: Application
    Filed: January 10, 2024
    Publication date: June 26, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tai-Cheng Hou, Da-Jun Lin, Bin-Siang Tsai, Fu-Yu Tsai, Ya-Yin Hsiao, Po-Ching Su, Yi-Fan Li, Kuan-Jhih Hou, Yu-Fu Wang, Ti-Bin Chen, Chih-Chiang Wu, Yao-Jhan Wang
  • Patent number: 12342594
    Abstract: Embodiments provide a semiconductor structure and a method for fabricating a semiconductor structure. The semiconductor structure includes: a source region and a drain region arranged at intervals on a substrate; a gate oxide layer arranged between the source region and the drain region; a gate structure arranged on the gate oxide layer; and a conductive plug arranged at a corresponding location of the source region and a corresponding location of the drain region. The gate structure includes a conductive layer having a recessed side surface facing toward the conductive plug. Compared with a traditional gate structure, in the solutions of the present disclosure, a distance between the conductive layer having the recessed side surface and the conductive plug is increased, thereby reducing a parasitic capacitance between the gate structure and the conductive plug, such that capacitances between a gate and the source/drain region are reduced, and device characteristics are improved.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: June 24, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Tieh-Chiang Wu, Lingxin Zhu
  • Publication number: 20250201564
    Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a metal layer is formed over a substrate using a fluorine-free deposition process, a nucleation layer is formed over the metal layer using a fluorine included deposition process, and a fill material is formed to fill an opening and form a gate stack.
    Type: Application
    Filed: March 5, 2025
    Publication date: June 19, 2025
    Inventors: Jung-Shiung Tsai, Chung-Chiang Wu, Wei-Fan Liao, Han-Ti Hsiaw
  • Patent number: 12336244
    Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a gate structure. The gate structure includes a gate dielectric layer, an n-type work function layer embedded in the gate dielectric layer, a dielectric capping layer embedded in the n-type work function layer, and a p-type work function layer embedded in the dielectric capping layer. A top surface of the gate structure exposes the n-type work function layer, the dielectric capping layer, and the p-type work function layer. The semiconductor structure also includes a first metal cap on the n-type work function layer and a second metal cap on the p-type work function layer. The first metal cap is spaced apart from the second metal cap. without formed on the dielectric capping layer.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: June 17, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Hang Chiu, Chung-Chiang Wu, Wei-Cheng Wang, Chia-Wei Chen, Jian-Hao Chen, Kuan-Ting Liu, Chi On Chui
  • Patent number: 12336172
    Abstract: Embodiments relate to the field of semiconductors, and provide a semiconductor structure and a fabricating method thereof. The semiconductor structure includes: a substrate (100), and a gate oxide layer (110) on a surface of the substrate (100); a gate stack layer (120) positioned on a surface of the gate oxide layer (110); a spacer(130) at least covering a first sidewall of the gate stack layer (120); a contact structure (140) at least positioned on the surface of the substrate (100); and a dielectric layer (150) at least positioned between the contact structure (140) and a second sidewall of the gate stack layer (120). The first sidewall and the second sidewall are arranged opposite to each other, and a thickness of the dielectric layer (150) is less than a thickness of the spacer(130). A breakdown difficulty of a fuse structure may be reduced at least.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: June 17, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Tieh-Chiang Wu, Lingxin Zhu
  • Publication number: 20250192080
    Abstract: An embodiment package comprises an integrated circuit die encapsulated in an encapsulant, a patch antenna over the integrated circuit die, and a dielectric feature disposed between the integrated circuit die and the patch antenna. The patch antenna overlaps the integrated circuit die in a top-down view. The thickness of the dielectric feature is in accordance with an operating bandwidth of the patch antenna.
    Type: Application
    Filed: February 19, 2025
    Publication date: June 12, 2025
    Inventors: Chen-Hua Yu, Kai-Chiang Wu, Chung-Shi Liu, Shou Zen Chang, Chao-Wen Shih
  • Publication number: 20250185344
    Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.
    Type: Application
    Filed: February 13, 2025
    Publication date: June 5, 2025
    Inventors: Chia-Ching Lee, Hsin-Han Tsai, Shih-Hang Chiu, Tsung-Ta Tang, Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Da-Yuan Lee, Jian-Hao Chen, Chien-Hao Chen, Kuo-Feng Yu, Chia-Wei Chen, Chih-Yu Hsu
  • Patent number: 12322691
    Abstract: A package structure includes a conductive feature structure, a die, an adhesive layer, an insulator, a through via, and an encapsulant. The die is disposed over the conductive feature structure. The adhesive layer is disposed below the die. The insulator is disposed between the adhesive layer and a polymer layer of the conductive feature structure. The through via extends through the insulator to connect to the conductive feature structure. The encapsulant is disposed on the insulator and the conductive feature structure, laterally encapsulating the die and the through via, and between the through via and the insulator. The insulator has a coefficient of thermal expansion less than a coefficient of thermal expansion of the encapsulant.
    Type: Grant
    Filed: January 24, 2024
    Date of Patent: June 3, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Chun-Lin Lu, Kai-Chiang Wu
  • Patent number: 12324212
    Abstract: Provided are a semiconductor structure and method for preparing same. The semiconductor structure includes a gate, a source or a drain being provided in the substrate at either side of the gate; a dielectric layer; a contact structure; a first electrical connection part and a second electrical connection part arranged at intervals. The second electrical connection part is in contact with a partial top surface of the contact structure. The first electrical connection part includes a first barrier layer and a first conductive layer which are stacked. In a direction from the source to the drain, a distance between the sidewall of the first barrier layer facing the contact structure and the contact structure is a first distance, and a distance between the sidewall of the first conductive layer facing the contact structure and the contact structure is a second distance, the first distance being greater than the second distance.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: June 3, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Tieh-Chiang Wu, Lingxin Zhu
  • Patent number: 12322670
    Abstract: An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: June 3, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Lin Lu, Kai-Chiang Wu, Yen-Ping Wang, Shih-Wei Liang, Ching-Feng Yang
  • Publication number: 20250159964
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.
    Type: Application
    Filed: January 15, 2025
    Publication date: May 15, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Fan Li, Wen-Yen Huang, Shih-Min Chou, Zhen Wu, Nien-Ting Ho, Chih-Chiang Wu, Ti-Bin Chen
  • Patent number: 12300733
    Abstract: A semiconductor device and method of manufacture are provided. In some embodiments a treatment process is utilized to treat a work function layer. The treatment prevents excessive oxidation of the work function layer during subsequent processing steps, such as application of a subsequent photoresist material, thereby allowing the work function layer to be thinner than otherwise.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: May 13, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ching Lee, Hung-Chin Chung, Chung-Chiang Wu, Hsuan-Yu Tung, Kuan-Chang Chiu, Chien-Hao Chen, Chi On Chui
  • Patent number: 12295178
    Abstract: An image sensor is provided. The image sensor includes a substrate, first photodiodes, second photodiodes, an interlayer, a light-guiding structure, and a micro-lens layer. The first photodiodes and the second photodiodes are alternately disposed in the substrate. The area of each of the first photodiodes is less than the area of each of the second photodiodes from a top view. The interlayer is disposed on the substrate. The light-guiding structure is disposed in the interlayer and over at least one of the first photodiodes or the second photodiodes. The refractive index of the light-guiding structure is greater than the refractive index of the interlayer. The micro-lens layer is disposed on the interlayer.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: May 6, 2025
    Assignee: VISERA TECHNOLOGIES COMPANY LIMITED
    Inventors: Yuan-Shuo Chang, Ching-Chiang Wu