Abstract: A method includes forming a function circuit on a semiconductor substrate of a device die, wherein the function circuit is in a functional circuit zone of the device die, forming a passive device over the semiconductor substrate, wherein the passive device is in a passive device zone of the device die, forming a first plurality of bond pads in the functional circuit zone and at a surface of the device die, wherein the first plurality of bond pads have a first pattern density; and forming a second plurality of bond pads in the passive device zone and at the surface of the device die. The second plurality of bond pads have a second pattern density lower than the first pattern density.

Abstract: An embodiment includes a method including forming a first interconnect structure over a first substrate, the first interconnect structure including dielectric layers and metallization patterns therein. The method also includes forming a redistribution via and a redistribution pad over the first interconnect structure, the redistribution via and the redistribution pad being electrically coupled to at least one of the metallization patterns of the first interconnect structure, the redistribution via and the redistribution pad having a same material composition. The method also includes forming a warpage control dielectric layer over the redistribution pad. The method also includes forming a bond via and a bond pad over the redistribution pad, the bond pad being in the warpage control dielectric layer, the bond via being electrically coupled to the redistribution pad.

Abstract: The present disclosure is directed to imaging LiDARs with optical antennas fed by optical waveguides. The optical antennas can be activated through an optical switch network that connects the optical antennas to a laser source to a receiver. A microlens array is positioned between a lens of the LiDAR system and the optical antennas, the microlens array being positioned so as to transform an emission angle from a corresponding optical antenna to match a chief ray angle of the lens. Methods of use and fabrication are also provided.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate including a base and a fin structure over the base. The fin structure includes a nanostructure. The semiconductor device structure includes a gate stack over the base and wrapped around the nanostructure. The gate stack has an upper portion and a sidewall portion, the upper portion is over the nanostructure, and the sidewall portion is over a first sidewall of the nanostructure. The semiconductor device structure includes a first inner spacer and a second inner spacer over opposite sides of the sidewall portion. A sum of a first width of the first inner spacer and a second width of the second inner spacer is greater than a third width of the sidewall portion as measured along a longitudinal axis of the fin structure.

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

Abstract: Provided is a circuit board structure including a substrate, a loop-wrapping ground layer, an insulating structure, a first build-up layer, a top wiring layer, a bottom wiring layer, a first conductive via, and a plurality of second conductive vias. The aforementioned structure defines a signal transmitting structure. An equivalent circuit of the signal transmitting structure at least includes a first equivalent circuit, a second equivalent circuit, a third equivalent circuit and a fourth equivalent circuit, which correspond to different uniform transmitting sections respectively. The first equivalent circuit, the second equivalent circuit, the third equivalent circuit and the fourth equivalent circuit are connected in series with each other according to an ABCD transmission matrix series connection principle.

Abstract: A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.

Abstract: An image sensor includes a first pixel array. The first pixel array includes multiple photo diodes and a polyhedron structure. The polyhedron structure is located above the photo diodes, and the polyhedron structure includes a bottom facet, a top facet, and at least one side facet. The bottom facet is located between the side facet and the photo diodes, and an orthogonal projection of the polyhedron structure overlaps with photo diodes. The polyhedron structure is configured to divide an incident light into a plurality of light beams focused in the photo diodes.

Abstract: A semiconductor includes a substrate. A gate structure is disposed on the substrate. A liner oxide contacts a side of the gate structure. A silicon oxide spacer contacts the liner oxide. An end of the silicon oxide spacer forms a kink profile. A silicon nitride spacer contacts the silicon oxide spacer and a tail of the silicon nitride spacer covers part of the kink profile. A stressor covers the silicon nitride spacer and the substrate.

Abstract: In various examples, a diagnostic circuit is connected to a target system to automatically trigger the target system to enter a diagnostic mode. The diagnostic circuit receives diagnostic data from the target system when the target system performs a diagnostic operation in the diagnostic mode.

Abstract: A device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.

Abstract: A large-scale silicon-photonics-based optical switching system that occupies an area larger than the maximum area of a standard step-and-repeat lithography reticle is disclosed. The system includes a plurality of identical switch blocks, each of is formed in a different reticle field that no larger than the maximum reticle size. Bus waveguides of laterally adjacent switch blocks are stitched together at lateral interfaces that include a second arrangement of waveguide ports that is common to all lateral interfaces. Bus waveguides of vertically adjacent switch blocks are stitched together at vertical interfaces that include a first arrangement of waveguide ports that is common to all vertical interfaces. In some embodiments, the lateral and vertical interfaces include waveguide ports having waveguide coupling regions that are configured to mitigate optical loss due to stitching error.

Abstract: Photonic integrated circuits (PICs) are provided that include silicon photonic structures such as a network of horizontal and vertical bus waveguides and micro-electro-mechanical-system (MEMS) actuated switching elements configured to selectively couple light between selected horizontal and vertical bus waveguides. The PICs of the present disclosure can be applied or used in a wide variety of fields including but not limited to fiber-optic communication, photonic computing, and light detection and ranging (LiDAR). The MEMS actuated switching elements can comprise piezoelectric actuators.

Abstract: A structure includes a die substrate; a passivation layer on the die substrate; first and second interconnect structures on the passivation layer; and a barrier on the passivation layer, at least one of the first or second interconnect structures, or a combination thereof. The first and second interconnect structures comprise first and second via portions through the passivation layer to first and second conductive features of the die substrate, respectively. The first and second interconnect structures further comprise first and second pads, respectively, and first and second transition elements on a surface of the passivation layer between the first and second via portion and the first and second pad, respectively. The barrier is disposed between the first pad and the second pad. The barrier does not fully encircle at least one of the first pad or the second pad.

Abstract: Photonic integrated circuits (PICs) are provided that include silicon photonic structures such as a network of horizontal and vertical bus waveguides and micro-electro-mechanical-system (MEMS) actuated switching elements configured to selectively couple light between selected horizontal and vertical bus waveguides. The PICs of the present disclosure can be applied or used in a wide variety of fields including but not limited to fiber-optic communication, photonic computing, and light detection and ranging (LiDAR). The PICs can include one or more planar lightwave circuit (PLC) die configured to evanescently couple one or more optical fibers to the plurality of silicon photonics structures.

Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.

Abstract: Apparatus and methods are provided for adaptively switching network connections based on scenario detection for slave mobile devices. In one embodiment, the slave mobile device monitors a plurality of sensor inputs and one or more high-layer configuration in a wide area wireless network, wherein the mobile device is configured with capabilities to keep communication to the wide area wireless network through a master device of a corresponding local connection network, generates a scenario indication based on a scenario matrix of the plurality of sensor inputs and the one or more high-layer configuration, and between the wide area wireless network and the local connection network upon determining a switch trigger based on the scenario indication and one or more lower-layer reports. In one embodiment, each indicated scenario is determined based on one or more factors including the one or more sensor inputs and the one or more high-layer configuration.

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.

Abstract: A method includes forming a gate dielectric on a semiconductor region, depositing a work-function layer over the gate dielectric, depositing a silicon layer over the work-function layer, and depositing a glue layer over the silicon layer. The work-function layer, the silicon layer, and the glue layer are in-situ deposited. The method further includes depositing a filling-metal over the glue layer; and performing a planarization process, wherein remaining portions of the glue layer, the silicon layer, and the work-function layer form portions of a gate electrode.

Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.