Patents by Inventor Chiang Wu
Chiang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12253729Abstract: A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.Type: GrantFiled: September 26, 2022Date of Patent: March 18, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Hsing-Kuo Hsia, Sung-Hui Huang, Kuan-Yu Huang, Kuo-Chiang Ting, Shang-Yun Hou, Chi-Hsi Wu
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Patent number: 12255104Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.Type: GrantFiled: August 2, 2023Date of Patent: March 18, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Ching Lee, Hsin-Han Tsai, Shih-Hang Chiu, Tsung-Ta Tang, Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Da-Yuan Lee, Jian-Hao Chen, Chien-Hao Chen, Kuo-Feng Yu, Chia-Wei Chen, Chih-Yu Hsu
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Patent number: 12256575Abstract: An image sensor includes a first pixel array. The first pixel array includes multiple photo diodes and a polyhedron structure. The polyhedron structure is located above the photo diodes, and the polyhedron structure includes a bottom facet, a top facet, and at least one side facet. The bottom facet is located between the side facet and the photo diodes, and an orthogonal projection of the polyhedron structure overlaps with photo diodes. The polyhedron structure is configured to divide an incident light into a plurality of light beams focused in the photo diodes.Type: GrantFiled: June 7, 2022Date of Patent: March 18, 2025Assignee: VisEra Technologies Company Ltd.Inventors: Shin-Hong Kuo, Yu-Chi Chang, Zong-Ru Tu, Ching-Chiang Wu, Po-Hsiang Wang
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Patent number: 12256488Abstract: Provided is a circuit board structure including a substrate, a loop-wrapping ground layer, an insulating structure, a first build-up layer, a top wiring layer, a bottom wiring layer, a first conductive via, and a plurality of second conductive vias. The aforementioned structure defines a signal transmitting structure. An equivalent circuit of the signal transmitting structure at least includes a first equivalent circuit, a second equivalent circuit, a third equivalent circuit and a fourth equivalent circuit, which correspond to different uniform transmitting sections respectively. The first equivalent circuit, the second equivalent circuit, the third equivalent circuit and the fourth equivalent circuit are connected in series with each other according to an ABCD transmission matrix series connection principle.Type: GrantFiled: February 1, 2023Date of Patent: March 18, 2025Assignee: Unimicron Technology Corp.Inventors: Chih-Chiang Lu, Jun-Rui Huang, Ming-Hao Wu, Tung-Chang Lin
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Publication number: 20250089334Abstract: A semiconductor includes a substrate. A gate structure is disposed on the substrate. A liner oxide contacts a side of the gate structure. A silicon oxide spacer contacts the liner oxide. An end of the silicon oxide spacer forms a kink profile. A silicon nitride spacer contacts the silicon oxide spacer and a tail of the silicon nitride spacer covers part of the kink profile. A stressor covers the silicon nitride spacer and the substrate.Type: ApplicationFiled: October 13, 2023Publication date: March 13, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yi-Fan Li, Chen-Ming Wang, Po-Ching Su, Pei-Hsun Kao, Ti-Bin Chen, Chun-Wei Yu, Chih-Chiang Wu
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Patent number: 12248392Abstract: In various examples, a diagnostic circuit is connected to a target system to automatically trigger the target system to enter a diagnostic mode. The diagnostic circuit receives diagnostic data from the target system when the target system performs a diagnostic operation in the diagnostic mode.Type: GrantFiled: February 28, 2022Date of Patent: March 11, 2025Assignee: NVIDIA CorporationInventors: Padmanabham Patki, Jue Wu, Chung-Hong Lai, Laurent Dahan, Marc Delvaux, Chiang Hsu
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Patent number: 12242108Abstract: A device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.Type: GrantFiled: December 1, 2023Date of Patent: March 4, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Hua Yu, Hsing-Kuo Hsia, Kuo-Chiang Ting, Sung-Hui Huang, Shang-Yun Hou, Chi-Hsi Wu
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Patent number: 12235492Abstract: A large-scale silicon-photonics-based optical switching system that occupies an area larger than the maximum area of a standard step-and-repeat lithography reticle is disclosed. The system includes a plurality of identical switch blocks, each of is formed in a different reticle field that no larger than the maximum reticle size. Bus waveguides of laterally adjacent switch blocks are stitched together at lateral interfaces that include a second arrangement of waveguide ports that is common to all lateral interfaces. Bus waveguides of vertically adjacent switch blocks are stitched together at vertical interfaces that include a first arrangement of waveguide ports that is common to all vertical interfaces. In some embodiments, the lateral and vertical interfaces include waveguide ports having waveguide coupling regions that are configured to mitigate optical loss due to stitching error.Type: GrantFiled: May 16, 2024Date of Patent: February 25, 2025Assignee: The Regents of the University of CaliforniaInventors: Tae Joon Seok, Ming Chiang A Wu
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Publication number: 20250042720Abstract: Photonic integrated circuits (PICs) are provided that include silicon photonic structures such as a network of horizontal and vertical bus waveguides and micro-electro-mechanical-system (MEMS) actuated switching elements configured to selectively couple light between selected horizontal and vertical bus waveguides. The PICs of the present disclosure can be applied or used in a wide variety of fields including but not limited to fiber-optic communication, photonic computing, and light detection and ranging (LiDAR). The MEMS actuated switching elements can comprise piezoelectric actuators.Type: ApplicationFiled: July 31, 2024Publication date: February 6, 2025Inventors: Tae Joon SEOK, Xiaosheng ZHANG, Ming Chiang A. WU, Noriaki KANEDA, Kyungmok KWON
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Patent number: 12218035Abstract: A structure includes a die substrate; a passivation layer on the die substrate; first and second interconnect structures on the passivation layer; and a barrier on the passivation layer, at least one of the first or second interconnect structures, or a combination thereof. The first and second interconnect structures comprise first and second via portions through the passivation layer to first and second conductive features of the die substrate, respectively. The first and second interconnect structures further comprise first and second pads, respectively, and first and second transition elements on a surface of the passivation layer between the first and second via portion and the first and second pad, respectively. The barrier is disposed between the first pad and the second pad. The barrier does not fully encircle at least one of the first pad or the second pad.Type: GrantFiled: April 4, 2022Date of Patent: February 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Chun Miao, Kai-Chiang Wu, Shih-Wei Liang
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Publication number: 20250035853Abstract: Photonic integrated circuits (PICs) are provided that include silicon photonic structures such as a network of horizontal and vertical bus waveguides and micro-electro-mechanical-system (MEMS) actuated switching elements configured to selectively couple light between selected horizontal and vertical bus waveguides. The PICs of the present disclosure can be applied or used in a wide variety of fields including but not limited to fiber-optic communication, photonic computing, and light detection and ranging (LiDAR). The PICs can include one or more planar lightwave circuit (PLC) die configured to evanescently couple one or more optical fibers to the plurality of silicon photonics structures.Type: ApplicationFiled: July 26, 2024Publication date: January 30, 2025Inventors: Tae Joon SEOK, Xiaosheng ZHANG, Ming Chiang A. WU, Noriaki KANEDA, Kyungmok KWON
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Patent number: 12211753Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.Type: GrantFiled: January 24, 2024Date of Patent: January 28, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sai-Hooi Yeong, Bo-Feng Young, Chi-On Chui, Chih-Chieh Yeh, Cheng-Hsien Wu, Chih-Sheng Chang, Tzu-Chiang Chen, I-Sheng Chen
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Publication number: 20250031101Abstract: Apparatus and methods are provided for adaptively switching network connections based on scenario detection for slave mobile devices. In one embodiment, the slave mobile device monitors a plurality of sensor inputs and one or more high-layer configuration in a wide area wireless network, wherein the mobile device is configured with capabilities to keep communication to the wide area wireless network through a master device of a corresponding local connection network, generates a scenario indication based on a scenario matrix of the plurality of sensor inputs and the one or more high-layer configuration, and between the wide area wireless network and the local connection network upon determining a switch trigger based on the scenario indication and one or more lower-layer reports. In one embodiment, each indicated scenario is determined based on one or more factors including the one or more sensor inputs and the one or more high-layer configuration.Type: ApplicationFiled: July 20, 2023Publication date: January 23, 2025Inventors: Fengyu Che, Jianwei Zhang, Nien-En Wu, Mingchun Chiang
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Publication number: 20250015158Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.Type: ApplicationFiled: September 18, 2024Publication date: January 9, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yi-Fan Li, Wen-Yen Huang, Shih-Min Chou, Zhen Wu, Nien-Ting Ho, Chih-Chiang Wu, Ti-Bin Chen
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Patent number: 12183638Abstract: A method includes forming a gate dielectric on a semiconductor region, depositing a work-function layer over the gate dielectric, depositing a silicon layer over the work-function layer, and depositing a glue layer over the silicon layer. The work-function layer, the silicon layer, and the glue layer are in-situ deposited. The method further includes depositing a filling-metal over the glue layer; and performing a planarization process, wherein remaining portions of the glue layer, the silicon layer, and the work-function layer form portions of a gate electrode.Type: GrantFiled: November 1, 2023Date of Patent: December 31, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Han Tsai, Chung-Chiang Wu, Cheng-Lung Hung, Weng Chang, Chi On Chui
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Patent number: 12183629Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.Type: GrantFiled: July 20, 2022Date of Patent: December 31, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Pin-Hsuan Yeh, Wei-Chin Lee, Hsien-Ming Lee, Chien-Hao Chen, Chi On Chui
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Publication number: 20240409393Abstract: MEMS optical circuit switches (OCS) are provided herein, which include novel structures and methods for (1) Alignment of the optical components (collimator array, micro-electromechanical systems (MEMS) mirror array, etc.) in a three-dimensional (3D) MEMS optical circuit switch OCS at the time of assembly or calibration; (2) Detection of the mechanical rotation angle of each MEMS mirror in a 3D MEMS OCS using strain sensors; (3) Monitoring and compensation of the long-term MEMS mirror rotation angle drift and system alignment drift of a 3D MEMS OCS; and (4) Fabrication and assembly of a 2-directional MEMS mirror with piezoelectric actuators.Type: ApplicationFiled: June 12, 2024Publication date: December 12, 2024Inventors: Xiaosheng ZHANG, Ming Chiang A. WU, Tae Joon SEOK, Kyungmok KWON, Noriaki KANEDA
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Patent number: 12155256Abstract: The present disclosure provides a fast charging driver. The fast charging driver is configured to charge a battery of an electronic device. The fast charging driver includes a fast charging circuit and a charging controller. The fast charging circuit includes a first depletion-type GaN transistor, a first enhancement-type field effect transistor, a second depletion-type GaN transistor and a second enhancement-type field effect transistor. The charging controller is configured to control the fast charging circuit to operate in a constant current mode or a constant voltage mode according to a battery level of the battery. By utilizing the first depletion-type GaN transistor and the second depletion-type GaN transistor with a characteristic of a relatively low switching loss, the power consumption during charging the battery by the fast charging driver is decreased to improve the charge speed.Type: GrantFiled: April 27, 2022Date of Patent: November 26, 2024Assignee: National Yang Ming Chiao Tung UniversityInventors: Edward Yi Chang, Stone Cheng, Wei-Hua Chieng, Shyr-Long Jeng, Chih-Chiang Wu
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Publication number: 20240387679Abstract: A semiconductor device and method of manufacture are provided. In some embodiments a treatment process is utilized to treat a work function layer. The treatment prevents excessive oxidation of the work function layer during subsequent processing steps, such as application of a subsequent photoresist material, thereby allowing the work function layer to be thinner than otherwise.Type: ApplicationFiled: July 29, 2024Publication date: November 21, 2024Inventors: Chia-Ching Lee, Hung-Chin Chung, Chung-Chiang Wu, Hsuan-Yu Tung, Kuan-Chang Chiu, Chien-Hao Chen, Chi On Chui
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Publication number: 20240387276Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.Type: ApplicationFiled: July 29, 2024Publication date: November 21, 2024Inventors: Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen, Ching-Hwanq Su