Patents by Inventor CHIAO-CHUN HSU
CHIAO-CHUN HSU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240018661Abstract: In some embodiments, a semiconductor fabrication tool is provided. The semiconductor fabrication tool includes a first heating plate arranged within a processing chamber and a second heating plate arranged within the processing chamber vertically over the first heating plate. A first exhaust port is arranged within the processing chamber and a second exhaust port arranged within the processing chamber vertically over the first exhaust port. The first exhaust port is in communication with the first heating plate and is coupled to a first exhaust output. The second exhaust port is in communication with the second heating plate and is coupled to a second exhaust output. A first control element is configured to control a first exhaust pressure at the first exhaust port and a second control element is configured to control a second exhaust pressure at the second exhaust port.Type: ApplicationFiled: July 24, 2023Publication date: January 18, 2024Inventors: Chiao-Chun Hsu, Chih-Ming Chen, Chung-Yi Yu, Sheng-Hsun Lu
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Publication number: 20240023445Abstract: In some embodiments, the present disclosure relates to a processing tool that includes a wafer chuck disposed within a hot plate chamber and having an upper surface is configured to hold a semiconductor wafer. A heating element is disposed within the wafer chuck and is configured to increase a temperature of the wafer chuck. A motor is coupled to the wafer chuck and configured to rotate the wafer chuck around an axis of rotation extending through the upper surface of the wafer chuck. The processing tool further includes control circuitry coupled to the motor and configured to operate the motor to rotate the wafer chuck while the temperature of the wafer chuck is increased to form a piezoelectric layer from a sol-gel solution layer on the semiconductor wafer.Type: ApplicationFiled: July 24, 2023Publication date: January 18, 2024Inventors: Chih-Ming Chen, Chiao-Chun Hsu, Chung-Yi Yu
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Patent number: 11869761Abstract: The present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within an image sensing die and respectively comprises a photodiode configured to convert radiation into an electrical signal. The photodiode comprises a photodiode doping column with a first doping type surrounded by a photodiode doping layer with a second doping type that is different than the first doping type. A BDTI structure is disposed between adjacent pixel regions and extending from the back-side of the image sensing die to a position within the photodiode doping layer. The BDTI structure comprises a doped liner with the second doping type and a dielectric fill layer. The doped liner lines a sidewall surface of the dielectric fill layer.Type: GrantFiled: September 11, 2020Date of Patent: January 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hung Cheng, Chun-Tsung Kuo, Jiech-Fun Lu, Min-Ying Tsai, Chiao-Chun Hsu, Ching I Li
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Patent number: 11832520Abstract: In some embodiments, the present disclosure relates to a processing tool that includes a wafer chuck disposed within a hot plate chamber and having an upper surface configured to hold a semiconductor wafer. A heating element is disposed within the wafer chuck and configured to increase a temperature of the wafer chuck. A motor is coupled to the wafer chuck and configured to rotate the wafer chuck around an axis of rotation extending through the upper surface of the wafer chuck. The processing tool further includes control circuitry coupled to the motor and configured to operate the motor to rotate the wafer chuck while the temperature of the wafer chuck is increased to form a piezoelectric layer from a sol-gel solution layer on the semiconductor wafer.Type: GrantFiled: April 27, 2021Date of Patent: November 28, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Ming Chen, Chiao-Chun Hsu, Chung-Yi Yu
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Patent number: 11814731Abstract: In some embodiments, a semiconductor fabrication tool is provided. The semiconductor fabrication tool includes a first processing zone having a first ambient environment and a second processing zone having a second ambient environment disposed at different location inside a processing chamber. A first exhaust port and a second exhaust port are disposed in the first and second processing zones, respectively. A first exhaust pipe couples the first exhaust port to a first individual exhaust output. A second exhaust pipe couples the second exhaust port to a second individual exhaust output, where the second exhaust pipe is separate from the first exhaust pipe. A first adjustable fluid control element controls the first ambient environment. A second adjustable fluid control element controls the second ambient environment, where the first adjustable fluid control element and the second adjustable fluid control element are independently adjustable.Type: GrantFiled: June 2, 2021Date of Patent: November 14, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chiao-Chun Hsu, Chih-Ming Chen, Chung-Yi Yu, Sheng-Hsun Lu
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Publication number: 20230066030Abstract: A calibration method for emulating a Group III-V semiconductor device, a method for determining trap location within a Group III-V semiconductor device and method for manufacturing a Group III-V semiconductor device are provided. Actual tape-out is performed according to an actual process flow of the Group III-V semiconductor device for manufacturing the Group III-V semiconductor devices and PCM Group III-V semiconductor device. Actual electrical performances of the Group III-V semiconductor devices and the PCM Group III-V semiconductor device are obtained and the actual electrical performances of the Group III-V semiconductor devices and the PCM Group III-V semiconductor device are compared to determine locations where one or more traps appear.Type: ApplicationFiled: August 31, 2021Publication date: March 2, 2023Inventors: CHIA-CHUNG CHEN, SHUFANG FU, KUAN-HUNG LIU, CHIAO-CHUN HSU, FU-YU SHIH, CHI-FENG HUANG, CHU FU CHEN
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Publication number: 20220384496Abstract: The present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within an image sensing die and respectively comprises a photodiode configured to convert radiation into an electrical signal. The photodiode comprises a photodiode doping column with a first doping type surrounded by a photodiode doping layer with a second doping type that is different than the first doping type. A BDTI structure is disposed between adjacent pixel regions and extending from the back-side of the image sensor die to a position within the photodiode doping layer. The BDTI structure comprises a doped liner with the second doping type and a dielectric fill layer. The doped liner lines a sidewall surface of the dielectric fill layer.Type: ApplicationFiled: August 9, 2022Publication date: December 1, 2022Inventors: Yu-Hung Cheng, Chun-Tsung Kuo, Jiech-Fun Lu, Min-Ying Tsai, Chiao-Chun Hsu, Ching I Li
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Publication number: 20220344575Abstract: In some embodiments, the present disclosure relates to a processing tool that includes a wafer chuck disposed within a hot plate chamber and having an upper surface configured to hold a semiconductor wafer. A heating element is disposed within the wafer chuck and configured to increase a temperature of the wafer chuck. A motor is coupled to the wafer chuck and configured to rotate the wafer chuck around an axis of rotation extending through the upper surface of the wafer chuck. The processing tool further includes control circuitry coupled to the motor and configured to operate the motor to rotate the wafer chuck while the temperature of the wafer chuck is increased to form a piezoelectric layer from a sol-gel solution layer on the semiconductor wafer.Type: ApplicationFiled: April 27, 2021Publication date: October 27, 2022Inventors: Chih-Ming Chen, Chiao-Chun Hsu, Chung-Yi Yu
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Publication number: 20220311357Abstract: In some embodiments, the present disclosure relates to a microelectromechanical system (MEMS) comb actuator including a comb structure. The comb structure includes a support layer having a first material and a plurality of protrusions extending away from a first surface of the support layer in a first direction. The plurality of protrusions are also made of the first material. The plurality of protrusions are separated along a second direction parallel to the first surface of the support layer. The MEMS comb actuator may further include a dielectric liner structure that continuously and completely covers the first surface of the support layer and outer surfaces of the plurality of protrusions. The dielectric liner structure includes a connective portion that continuously connects topmost surfaces of at least two of the plurality of protrusions.Type: ApplicationFiled: June 16, 2022Publication date: September 29, 2022Inventors: Chiao-Chun Hsu, Chih-Ming Chen, Chung-Yi Yu, Lung Yuan Pan
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Patent number: 11387748Abstract: In some embodiments, the present disclosure relates to a microelectromechanical system (MEMS) comb actuator including a comb structure. The comb structure includes a support layer having a first material and a plurality of protrusions extending away from a first surface of the support layer in a first direction. The plurality of protrusions are also made of the first material. The plurality of protrusions are separated along a second direction parallel to the first surface of the support layer. The MEMS comb actuator may further include a dielectric liner structure that continuously and completely covers the first surface of the support layer and outer surfaces of the plurality of protrusions. The dielectric liner structure includes a connective portion that continuously connects topmost surfaces of at least two of the plurality of protrusions.Type: GrantFiled: February 26, 2020Date of Patent: July 12, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chiao-Chun Hsu, Chih-Ming Chen, Chung-Yi Yu, Lung Yuan Pan
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Publication number: 20210335861Abstract: The present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within an image sensing die and respectively comprises a photodiode configured to convert radiation into an electrical signal. The photodiode comprises a photodiode doping column with a first doping type surrounded by a photodiode doping layer with a second doping type that is different than the first doping type. A BDTI structure is disposed between adjacent pixel regions and extending from the back-side of the image sensing die to a position within the photodiode doping layer. The BDTI structure comprises a doped liner with the second doping type and a dielectric fill layer. The doped liner lines a sidewall surface of the dielectric fill layer.Type: ApplicationFiled: September 11, 2020Publication date: October 28, 2021Inventors: Yu-Hung Cheng, Chun-Tsung Kuo, Jiech-Fun Lu, Min-Ying Tsai, Chiao-Chun Hsu, Ching I Li
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Publication number: 20210285107Abstract: In some embodiments, a semiconductor fabrication tool is provided. The semiconductor fabrication tool includes a first processing zone having a first ambient environment and a second processing zone having a second ambient environment disposed at different location inside a processing chamber. A first exhaust port and a second exhaust port are disposed in the first and second processing zones, respectively. A first exhaust pipe couples the first exhaust port to a first individual exhaust output. A second exhaust pipe couples the second exhaust port to a second individual exhaust output, where the second exhaust pipe is separate from the first exhaust pipe. A first adjustable fluid control element controls the first ambient environment. A second adjustable fluid control element controls the second ambient environment, where the first adjustable fluid control element and the second adjustable fluid control element are independently adjustable.Type: ApplicationFiled: June 2, 2021Publication date: September 16, 2021Inventors: Chiao-Chun Hsu, Chih-Ming Chen, Chung-Yi Yu, Sheng-Hsun Lu
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Patent number: 11047050Abstract: In some embodiments, a semiconductor fabrication tool is provided. The semiconductor fabrication tool includes a first processing zone having a first ambient environment and a second processing zone having a second ambient environment disposed at different location inside a processing chamber. A first exhaust port and a second exhaust port are disposed in the first and second processing zones, respectively. A first exhaust pipe couples the first exhaust port to a first individual exhaust output. A second exhaust pipe couples the second exhaust port to a second individual exhaust output, where the second exhaust pipe is separate from the first exhaust pipe. A first adjustable fluid control element controls the first ambient environment. A second adjustable fluid control element controls the second ambient environment, where the first adjustable fluid control element and the second adjustable fluid control element are independently adjustable.Type: GrantFiled: March 13, 2019Date of Patent: June 29, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chiao-Chun Hsu, Chih-Ming Chen, Chung-Yi Yu, Sheng-Hsun Lu
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Publication number: 20210067058Abstract: In some embodiments, the present disclosure relates to a microelectromechanical system (MEMS) comb actuator including a comb structure. The comb structure includes a support layer having a first material and a plurality of protrusions extending away from a first surface of the support layer in a first direction. The plurality of protrusions are also made of the first material. The plurality of protrusions are separated along a second direction parallel to the first surface of the support layer. The MEMS comb actuator may further include a dielectric liner structure that continuously and completely covers the first surface of the support layer and outer surfaces of the plurality of protrusions. The dielectric liner structure includes a connective portion that continuously connects topmost surfaces of at least two of the plurality of protrusions.Type: ApplicationFiled: February 26, 2020Publication date: March 4, 2021Inventors: Chiao-Chun Hsu, Chih-Ming Chen, Chung-Yi Yu, Lung Yuan Pan
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Publication number: 20200131641Abstract: In some embodiments, a semiconductor fabrication tool is provided. The semiconductor fabrication tool includes a first processing zone having a first ambient environment and a second processing zone having a second ambient environment disposed at different location inside a processing chamber. A first exhaust port and a second exhaust port are disposed in the first and second processing zones, respectively. A first exhaust pipe couples the first exhaust port to a first individual exhaust output. A second exhaust pipe couples the second exhaust port to a second individual exhaust output, where the second exhaust pipe is separate from the first exhaust pipe. A first adjustable fluid control element controls the first ambient environment. A second adjustable fluid control element controls the second ambient environment, where the first adjustable fluid control element and the second adjustable fluid control element are independently adjustable.Type: ApplicationFiled: March 13, 2019Publication date: April 30, 2020Inventors: Chiao-Chun Hsu, Chih-Ming Chen, Chung-Yi Yu, Sheng-Hsun Lu
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Publication number: 20150036564Abstract: A method to decrease power consumption of a plurality of end devices in a wireless network system divides a round period into at least a first period and a second period, each of the periods having multiple time slots. The wireless network system is formed by an access point, a plurality of routers and a plurality of end devices, forming a two-layer tree network topology. The method comprises: a) wirelessly broadcasting one router beacon in each of the time slots of the first period from one of the routers to the router's end devices; b) determining if any end device fails to receive any router beacon transmitted from its parent node in the first period; and c) configuring the end device to sleep during the second period if it fails to receive any router beacon transmitted from its parent node in the first period.Type: ApplicationFiled: July 31, 2013Publication date: February 5, 2015Applicant: M+hu 2+l COMMUNICATION, INC.Inventors: CHUN-YU CHEN, CHIAO-CHUN HSU, YU-JEN LIN, CHUN-KAI WEI
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Publication number: 20150036565Abstract: A method to decrease power consumption of a plurality of end devices in a wireless network system divides a round period into at least a first period and a second period, each of the periods having multiple time slots. The wireless network system is formed by an access point, a plurality of routers and a plurality of end devices, forming a two-layer tree network topology. The method comprising: a) wirelessly broadcasting a null beacon from one of the routers to the router's end devices in the first period if the router fails receive an AP beacon from the access point in the first period; and b) configuring the router's end devices to sleep during the second period after the router's end devices receive the null beacon from the router.Type: ApplicationFiled: July 31, 2013Publication date: February 5, 2015Applicant: M²Communication, Inc.Inventors: CHUN-YU CHEN, CHIAO-CHUN HSU, YU-JEN LIN, CHUN-KAI WEI
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Publication number: 20150036649Abstract: A wireless network system utilizing dual frequencies comprises an access point having a first communication module, wherein the first communication module transmits downlink data and receives uplink data wirelessly in a first frequency; a plurality of routers, each having a second communication module, wherein the second communication module receives the downlink data from the access point and transmits the uplink data to the access point wirelessly in the first frequency and transmits the downlink data and receives the uplink data wirelessly in a second frequency; and a plurality of end devices, each having a third communication module, wherein the third communication module receives the downlink data from one of the plurality of routers and transmits the uplink data to the same one of the plurality of routers wirelessly in the second frequency.Type: ApplicationFiled: July 31, 2013Publication date: February 5, 2015Applicant: M²COMMUNICATION, INC.Inventors: CHUN-YU CHEN, CHIAO-CHUN HSU, YU-JEN LIN, CHUN-KAI WEI