Patents by Inventor Chiao-Han LEE

Chiao-Han LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230378169
    Abstract: The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device comprises a substrate, a first gate electrode, a second gate electrode, a first doped region, a second doped region, a third doped region, and a first interconnection structure. The substrate comprises a well region of a first conductive type. The first and second gate electrodes are disposed on the substrate. The first, second, and third doped regions are embedded within the well region and are of the first conductive type. The first interconnection structure electrically connects the first gate electrode and the second gate electrode. The first doped region and the second doped region are disposed on opposite sides of the first gate electrode.
    Type: Application
    Filed: May 18, 2022
    Publication date: November 23, 2023
    Inventors: HO-HSIANG CHEN, CHI-HSIEN LIN, YING-TA LU, HSIEN-YUAN LIAO, HSIU-WEN WU, CHIAO-HAN LEE, TZU-JIN YEH
  • Patent number: 11817385
    Abstract: An integrated circuit includes an inductor that includes a first set of conductive lines in a first metal layer, and is over a substrate, and a guard ring. The guard ring includes a first conductive line in a second metal layer, and extending in a first direction, a second conductive line extending in a second direction, and a first staggered line coupled between the first conductive line and the second conductive line. The first staggered line includes a second set of conductive lines in the second metal layer, and extends in the first direction, a third set of conductive lines in a third metal layer, and extends in the second direction, and a first set of vias coupling the second and third set of conductive lines together. All metal lines in the third metal layer that are part of the guard ring extend in the second direction.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: November 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chiao-Han Lee, Chi-Hsien Lin, Ho-Hsiang Chen, Hsien-Yuan Liao, Tzu-Jin Yeh, Ying-Ta Lu
  • Publication number: 20230282644
    Abstract: A cell layout design for an integrated circuit. In one embodiment, the integrated circuit includes a dual-gate cell forming two transistors connected with each other via a common source/drain terminal. The dual-gate cell includes an active region, two gate lines extending across the active region, at least one first gate via disposed on one or both of the two gate lines and overlapped with the active region, and second gate vias disposed on one or both of the two gate lines and located outside the active region.
    Type: Application
    Filed: June 30, 2022
    Publication date: September 7, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ho-Hsiang CHEN, Chi-Hsien LIN, Ying-Ta LU, Hsien-Yuan LIAO, Hsiu-Wen WU, Chiao-Han LEE, Tzu-Jin YEH
  • Publication number: 20210358844
    Abstract: An integrated circuit includes an inductor that includes a first set of conductive lines in a first metal layer, and is over a substrate, and a guard ring. The guard ring includes a first conductive line in a second metal layer, and extending in a first direction, a second conductive line extending in a second direction, and a first staggered line coupled between the first conductive line and the second conductive line. The first staggered line includes a second set of conductive lines in the second metal layer, and extends in the first direction, a third set of conductive lines in a third metal layer, and extends in the second direction, and a first set of vias coupling the second and third set of conductive lines together. All metal lines in the third metal layer that are part of the guard ring extend in the second direction.
    Type: Application
    Filed: July 30, 2021
    Publication date: November 18, 2021
    Inventors: Chiao-Han LEE, Chi-Hsien LIN, Ho-Hsiang CHEN, Hsien-Yuan LIAO, Tzu-Jin YEH, Ying-Ta LU
  • Patent number: 11081444
    Abstract: An integrated circuit includes an inductor over a substrate and a guard ring surrounding the inductor. The guard ring includes a first staggered line, a first metal line extending in a first direction and a second metal line extending in a second direction different from the first direction. The first staggered line has a first end coupled to the first metal line, and a second end coupled to the second metal line. The first staggered line includes a first set of vias, a first set of metal lines in a first metal layer and a second set of metal lines in a second metal layer different from the first metal layer. The first set of vias coupling the first set of metal lines with the second of second metal lines.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: August 3, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chiao-Han Lee, Hsien-Yuan Liao, Ying-Ta Lu, Chi-Hsien Lin, Ho-Hsiang Chen, Tzu-Jin Yeh
  • Publication number: 20190103354
    Abstract: An integrated circuit includes an inductor over a substrate and a guard ring surrounding the inductor. The guard ring includes a first staggered line, a first metal line extending in a first direction and a second metal line extending in a second direction different from the first direction. The first staggered line has a first end coupled to the first metal line, and a second end coupled to the second metal line. The first staggered line includes a first set of vias, a first set of metal lines in a first metal layer and a second set of metal lines in a second metal layer different from the first metal layer. The first set of vias coupling the first set of metal lines with the second of second metal lines.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 4, 2019
    Inventors: Chiao-Han LEE, Hsien-Yuan LIAO, Ying-Ta LU, Chi-Hsien LIN, Ho-Hsiang CHEN, Tzu-Jin YEH
  • Patent number: 10163779
    Abstract: An integrated circuit comprises an inductor over a substrate and a guard ring surrounding the inductor. The guard ring comprises a plurality of first metal lines extending in a first direction and a plurality of second metal lines extending in a second direction. The second metal lines of the plurality of second metal lines are each coupled with at least one first metal line of the plurality of first metal lines. The guard ring also comprises a staggered line comprising a connected subset of at least one first metal line of the plurality of first metal lines and at least one second metal line of the plurality of second metal lines. The first metal lines of the plurality of first metal lines outside of the connected subset, the second metal lines of the plurality of second metal lines outside of the connected subset, and the staggered line surround the inductor.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chiao-Han Lee, Hsien-Yuan Liao, Ying-Ta Lu, Chi-Hsien Lin, Ho-Hsiang Chen, Tzu-Jin Yeh
  • Publication number: 20150364417
    Abstract: An integrated circuit comprises an inductor over a substrate and a guard ring surrounding the inductor. The guard ring comprises a plurality of first metal lines extending in a first direction and a plurality of second metal lines extending in a second direction. The second metal lines of the plurality of second metal lines are each coupled with at least one first metal line of the plurality of first metal lines. The guard ring also comprises a staggered line comprising a connected subset of at least one first metal line of the plurality of first metal lines and at least one second metal line of the plurality of second metal lines. The first metal lines of the plurality of first metal lines outside of the connected subset, the second metal lines of the plurality of second metal lines outside of the connected subset, and the staggered line surround the inductor.
    Type: Application
    Filed: June 12, 2014
    Publication date: December 17, 2015
    Inventors: Chiao-Han LEE, Hsien-Yuan LIAO, Ying-Ta LU, Chi-Hsien LIN, Ho-Hsiang CHEN, Tzu-Jin YEH
  • Patent number: 8797104
    Abstract: A low-noise amplifier includes a first transistor having a gate configured to receive an oscillating input signal and a source coupled to ground. A second transistor has a source coupled to a drain of the first transistor, a gate coupled to a bias voltage, and a drain coupled to an output node. At least one of the first and second transistors includes a floating deep n-well that is coupled to an isolation circuit.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: August 5, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsieh-Hung Hsieh, Yi-Hsuan Liu, Chiao-Han Lee, Tzu-Jin Yeh, Chewn-Pu Jou
  • Publication number: 20130271223
    Abstract: A low-noise amplifier includes a first transistor having a gate configured to receive an oscillating input signal and a source coupled to ground. A second transistor has a source coupled to a drain of the first transistor, a gate coupled to a bias voltage, and a drain coupled to an output node. At least one of the first and second transistors includes a floating deep n-well that is coupled to an isolation circuit.
    Type: Application
    Filed: April 13, 2012
    Publication date: October 17, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsieh-Hung HSIEH, Yi-Hsuan LIU, Chiao-Han LEE, Tzu-Jin YEH, Chewn-Pu JOU