Patents by Inventor Chiao Kai Hwang
Chiao Kai Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9170775Abstract: A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs) of data representing zero can be input to the MAC block and sent directly to the add-subtract-accumulate unit. Alternatively, dedicated configuration bits can be set to clear the contents of a pipeline register for input to the add-subtract-accumulate unit.Type: GrantFiled: January 7, 2010Date of Patent: October 27, 2015Assignee: Altera CorporationInventors: Leon Zheng, Martin Langhammer, Nitin Prasad, Greg Starr, Chiao Kai Hwang, Kumara Tharmalingam
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Patent number: 8364738Abstract: In a programmable logic device having a specialized functional block incorporating multipliers and adders, multiplication operations that do not fit neatly into the available multipliers are performed partially in the multipliers of the specialized functional block and partially in multipliers configured in programmable logic of the programmable logic device. Unused resources of the specialized functional block, including adders, may be used to add together the partial products produced inside and outside the specialized functional block. Some adders configured in programmable logic of the programmable logic device also may be used for that purpose.Type: GrantFiled: March 2, 2010Date of Patent: January 29, 2013Assignee: Altera CorporationInventors: Martin Langhammer, Leon Zheng, Chiao Kai Hwang, Gregory Starr
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Patent number: 7800405Abstract: Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE-Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.Type: GrantFiled: June 15, 2009Date of Patent: September 21, 2010Assignee: Altera CorporationInventors: Andy L. Lee, Wanli Chang, Cameron McClintock, John E. Turner, Brian D. Johnson, Chiao Kai Hwang, Richard Yen-Hsiang Chang, Richard G. Cliff
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Publication number: 20100169404Abstract: A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs) of data representing zero can be input to the MAC block and sent directly to the add-subtract-accumulate unit. Alternatively, dedicated configuration bits can be set to clear the contents of a pipeline register for input to the add-subtract-accumulate unit.Type: ApplicationFiled: January 7, 2010Publication date: July 1, 2010Inventors: Leon Zheng, Martin Langhammer, Nitin Prasad, Greg Starr, Chiao Kai Hwang, Kumara Tharmalingam
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Patent number: 7698358Abstract: In a programmable logic device having a specialized functional block incorporating multipliers and adders, multiplication operations that do not fit neatly into the available multipliers are performed partially in the multipliers of the specialized functional block and partially in multipliers configured in programmable logic of the programmable logic device. Unused resources of the specialized functional block, including adders, may be used to add together the partial products produced inside and outside the specialized functional block. Some adders configured in programmable logic of the programmable logic device also may be used for that purpose.Type: GrantFiled: December 24, 2003Date of Patent: April 13, 2010Assignee: Altera CorporationInventors: Martin Langhammer, Leon Zheng, Chiao Kai Hwang, Gregory Starr
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Patent number: 7660841Abstract: A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs) of data representing zero can be input to the MAC block and sent directly to the add-subtract-accumulate unit. Alternatively, dedicated configuration bits can be set to clear the contents of a pipeline register for input to the add-subtract-accumulate unit.Type: GrantFiled: February 20, 2004Date of Patent: February 9, 2010Assignee: Altera CorporationInventors: Leon Zheng, Martin Langhammer, Nitin Prasad, Greg Starr, Chiao Kai Hwang, Kumara Tharmalingam
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Publication number: 20090267645Abstract: Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE-Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.Type: ApplicationFiled: June 15, 2009Publication date: October 29, 2009Applicant: Altera CorporationInventors: Andy L. Lee, Wanli Chang, Cameron McClintock, John E. Turner, Brian D. Johnson, Chiao Kai Hwang, Richard Yen-Hsiang Chang, Richard G. Cliff
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Patent number: 7557608Abstract: Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE-Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.Type: GrantFiled: August 1, 2006Date of Patent: July 7, 2009Assignee: Altera CorporationInventors: Andy L Lee, Wanli Chang, Cameron McClintock, John E Turner, Brian D Johnson, Chiao Kai Hwang, Richard Yen-Hsiang Chang, Richard G Cliff
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Patent number: 7346644Abstract: A programmable logic integrated circuit device (“PLD”) includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly inefficient to implement in the more general-purpose programmable logic and/or that, if implemented in the programmable logic, would operate unacceptably or at least undesirably slowly. The digital signal processing region may include multiple digital signal processing stages. The digital signal processing region may include a multiplier stage and one or more stages that can operate in combination with the multiplier stage. The digital signal processing region has a plurality of modes such as for providing multiply-and-accumulate operation, multiply-and-add operation, etc.Type: GrantFiled: August 17, 2006Date of Patent: March 18, 2008Assignee: Altera CorporationInventors: Martin Langhammer, Gregory Starr, Chiao Kai Hwang
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Patent number: 7216139Abstract: In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers. Those scan chain registers are ANDed with the input registers, and can be loaded with templates of ones and zeroes. This allows, e.g., subset multiplication if the least significant bits are loaded with zeroes and the remaining bits are loaded with ones. The multipliers preferably are arranged in blocks with other components, such as adders, that allow them to be configured as finite impulse response (FIR) filters. In such configurations, the scan chain registers can be used to load filter coefficients, avoiding the use of scarce logic and routing resources of the device.Type: GrantFiled: December 28, 2005Date of Patent: May 8, 2007Assignee: Altera CorporationInventors: Martin Langhammer, Chiao Kai Hwang, Gregory Starr
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Patent number: 7142010Abstract: In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers. Those scan chain registers are ANDed with the input registers, and can be loaded with templates of ones and zeroes. This allows, e.g., subset multiplication if the least significant bits are loaded with zeroes and the remaining bits are loaded with ones. The multipliers preferably are arranged in blocks with other components, such as adders, that allow them to be configured as finite impulse response (FIR) filters. In such configurations, the scan chain registers can be used to load filter coefficients, avoiding the use of scarce logic and routing resources of the device.Type: GrantFiled: December 19, 2003Date of Patent: November 28, 2006Assignee: Altera CorporationInventors: Martin Langhammer, Chiao Kai Hwang, Gregory Starr
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Patent number: 7119574Abstract: Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE?Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.Type: GrantFiled: August 8, 2003Date of Patent: October 10, 2006Assignee: Altera CorporationInventors: Andy L Lee, Wanli Chang, Cameron McClintock, John E Turner, Brian D Johnson, Chiao Kai Hwang, Richard Y Chang, Richard G Cliff
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Patent number: 7119576Abstract: A programmable logic integrated circuit device (“PLD”) includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly inefficient to implement in the more general-purpose programmable logic and/or that, if implemented in the programmable logic, would operate unacceptably or at least undesirably slowly. The digital signal processing region may include multiple digital signal processing stages. The digital signal processing region may include a multiplier stage and one ore more stages that can operate in combination with the multiplier stage. The digital signal processing region has a plurality of modes such as for providing multiply-and-accumulate operation, multiply-and-add operation, etc.Type: GrantFiled: June 18, 2004Date of Patent: October 10, 2006Assignee: Altera CorporationInventors: Martin Langhammer, Gregory Starr, Chiao Kai Hwang
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Patent number: 6958624Abstract: A bypassable latch circuit consumes less power in the bypass mode than it does in the latched mode. The circuit includes a flip-flop whose output is routed to an input of a multiplexer. The other input of the multiplexer is the input of the flip-flop as well. The multiplexer is used to select as the latch output either the registered or latched flip-flop output, or the flip-flop input. The flip-flop is modified by replacing the inverter at the flip-flop clock input with a logic gate that accepts as inputs both the clock input and a control input. The control input can cause the flip-flop to ignore the clock, preventing switching that consumes power by charging and discharging capacitive elements in the flip-flop.Type: GrantFiled: May 12, 2003Date of Patent: October 25, 2005Assignee: Altera CorporationInventors: Gregory Starr, Martin Langhammer, Chiao Kai Hwang
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Patent number: 6937062Abstract: In a specialized functional region of a programmable logic device, in which certain components may not be used, those components can be placed in a low-power mode so that they do not switch. For example, in an adder which is not being used but is receiving inputs, the current path for the adding circuitry is interrupted, while the output is forced low. If the adder is a carry/look-ahead adder, the GENERATE and PROPAGATE signals normally used in subsequent stages to predict the value of the carry signal are forced to constant values even if the inputs to the adder are changing.Type: GrantFiled: February 12, 2004Date of Patent: August 30, 2005Assignee: Altera CorporationInventors: Chiao Kai Hwang, Gregory Starr, Martin Langhammer
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Patent number: 6771094Abstract: A programmable logic integrated circuit device (“PLD”) includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly inefficient to implement in the more general-purpose programmable logic and/or that, if implemented in the programmable logic, would operate unacceptably or at least undesirably slowly. The digital signal processing region may include multiple digital signal processing stages. The digital signal processing region may include a multiplier stage and one ore more stages that can operate in combination with the multiplier stage. The digital signal processing region has a plurality of modes such as for providing multiply-and-accumulate operation, multiply-and-add operation, etc.Type: GrantFiled: January 28, 2003Date of Patent: August 3, 2004Assignee: Altera CorporationInventors: Martin Langhammer, Gregory Starr, Chiao Kai Hwang
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Patent number: 6714042Abstract: In a specialized functional region of a programmable logic device, in which certain components may not be used, those components can be placed in a low-power mode so that they do not switch. For example, in an adder which is not being used but is receiving inputs, the current path for the adding circuitry is interrupted, while the output is forced low. If the adder is a carry/look-ahead adder, the GENERATE and PROPAGATE signals normally used in subsequent stages to predict the value of the carry signal are forced to constant values even if the inputs to the adder are changing.Type: GrantFiled: March 6, 2003Date of Patent: March 30, 2004Assignee: Altera CorporationInventors: Chiao Kai Hwang, Gregory Starr, Martin Langhammer
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Patent number: 6693455Abstract: In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers. Those scan chain registers are ANDed with the input registers, and can be loaded with templates of ones and zeroes. This allows, e.g., subset multiplication if the least significant bits are loaded with zeroes and the remaining bits are loaded with ones. The multipliers preferably are arranged in blocks with other components, such as adders, that allow them to be configured as finite impulse response (FIR) filters. In such configurations, the scan chain registers can be used to load filter coefficients, avoiding the use of scarce logic and routing resources of the device.Type: GrantFiled: February 26, 2003Date of Patent: February 17, 2004Assignee: Altera CorporationsInventors: Martin Langhammer, Chiao Kai Hwang, Gregory Starr
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Patent number: 6661253Abstract: Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE−Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.Type: GrantFiled: August 16, 2001Date of Patent: December 9, 2003Assignee: Altera CorporationInventors: Andy L. Lee, Wanli Chang, Cameron McClintock, John E. Turner, Brian D. Johnson, Chiao Kai Hwang, Richard Yen-Hsiang Chang, Richard G. Cliff
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Publication number: 20030128049Abstract: In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers. Those scan chain registers are ANDed with the input registers, and can be loaded with templates of ones and zeroes. This allows, e.g., subset multiplication if the least significant bits are loaded with zeroes and the remaining bits are loaded with ones. The multipliers preferably are arranged in blocks with other components, such as adders, that allow them to be configured as finite impulse response (FIR) filters. In such configurations, the scan chain registers can be used to load filter coefficients, avoiding the use of scarce logic and routing resources of the device.Type: ApplicationFiled: February 26, 2003Publication date: July 10, 2003Applicant: ALTERA CORPORATION, a corporation of DelawareInventors: Martin Langhammer, Chiao Kai Hwang, Gregory Starr