Abstract: A display device and a method for detecting an ESD phenomenon are provided. The method including: encoding image data according to an encoding operation to generate a check code; sending the image data and the check code to a receiver by a transmitter, and obtaining a receiving image data and a receiving check code by the receiver; encoding the receiving image data according to the encoding operation to generate a verification check code; and determining whether the ESD phenomenon is occurred by comparing the check code and the verification check code.

Abstract: A method for driving a display includes a host transmitting a plurality of dynamic frame images to the display, a display panel of the display displaying the plurality of dynamic frame images according to a first gamma table, the host activating a panel self refresh function of the display, and the display panel displaying at least one prior frame image according to a second gamma table after the panel self refresh function is activated. The same grey scale in the first gamma table and the second gamma table corresponds to different gamma voltages. The prior frame images are stored in a memory of the display, and the at least one prior frame image includes at least one dynamic frame image of the plurality of dynamic frame images.

Abstract: A display apparatus and a driving method for the display panel thereof are provided. The timing controller of the display apparatus determines whether the frame-displaying signal is a specific frame for displaying a first gray-level value and a second gray-level value. When the frame-displaying signal is corresponding to a specific frame for displaying the first gray-level value and the second gray-level value, the timing controller adjusts a plurality of enabling durations of multiple scan signals to control the pixels displaying the same luminance; when the frame-displaying signal is not corresponding to the specific frame for displaying the first gray-level value and the second gray-level value, the timing controller adjusts the enabling time of the scan signals to be identical to each other.

Abstract: A display clip system and a timing clip control method thereof are provided. The clip system is connected to a gate driver circuit, and includes a timing controller and a clip module. According to a system input signal and its frame rates, the timing controller generates an enable signal, a clip trigger signal, and a base working signal. The clip module adjusts the base working signal by using the enable signal and the clip trigger signal. Then, the base working signal carries a first clip voltage to output to the gate driver circuit. When the frame rate changes, the timing controller adjusts trigger points and trigger time lengths of the enable signal and the clip trigger signal, and the clip module adjusts the base working signal. Then, the base working signal carries a second clip voltage equal to the first clip voltage to output to the gate driver circuit.

Abstract: A display clip system and a timing clip control method thereof are provided. The clip system is connected to a gate driver circuit, and includes a timing controller and a clip module. According to a system input signal and it's frame rates, the timing controller generates an enable signal, a clip trigger signal, and a base working signal. The clip module adjusts the base working signal by using the enable signal and the clip trigger signal. Then, the base working signal carries a first clip voltage to output to the gate driver circuit. When the frame rate changes, the timing controller adjusts trigger points and trigger time lengths of the enable signal and the clip trigger signal, and the clip module adjusts the base working signal. Then, the base working signal carries a second clip voltage equal to the first clip voltage to output to the gate driver circuit.

Abstract: The present invention discloses an source driver circuit scheme for displayer, which comprises a shifter register to register data signal, a line buffer coupled with said shifter register to latch the data signal, a level shifter coupled with line buffer to level output electrical potential, a digital-to-analog converter (DAC) to convert digital signal to analog signal, an output buffer coupled with said digital-to-analog converter (DAC) to output converted signal, and an output control circuit coupled with output buffer. Said output control circuit comprises a D flip-flop and CMOS switching element to output a LP_out signal and control the data signal output of the source driver IC to avoid the power-on noise of the displayer.

Abstract: A driving method for a display panel is provided. The driving method includes detecting whether the display panel switches between frames; and down-regulating/up-regulating the frame rate of the display panel and adjusting the voltage value of a gate-on power source when the display panel switches from a dynamic frame to a static frame or switches from the static frame to the dynamic frame, so as to change a charging current of pixels in the display panel.

Abstract: An apparatus and method of driving a display panel are provided. The apparatus includes a comparison unit and a source driver. The comparison unit receives and stores a current line data, and compares the current line data with a previous stored line data. When a pixel data within the current line data and another pixel data within the previous line data at the same position are not identical, the comparison unit outputs the pixel data of the current line data, and the source driver latches the pixel data for driving the display panel, which is output from the comparison unit. When the pixel data within the current line data and another pixel data within the previous line data at the same position are not identical, the comparison unit does not output the pixel data, and the source driver drives the display panel in accordance with the previously latched pixel data.

Abstract: The present invention discloses an source driver circuit scheme for displayer, which comprises a shifter register to register data signal, a line buffer coupled with said shifter register to latch the data signal, a level shifter coupled with line buffer to level output electrical potential, a digital-to-analog converter (DAC) to convert digital signal to analog signal, an output buffer coupled with said digital-to-analog converter (DAC) to output converted signal, and an output control circuit coupled with output buffer. Said output control circuit comprises a D flip-flop and CMOS switching element to output a LP_out signal and control the data signal output of the source driver IC to avoid the power-on noise of the displayer.