Patents by Inventor Chiao-Lun Tsai

Chiao-Lun Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10657080
    Abstract: A system and method for insuring efficiency of a serial link between a host server and a switch is disclosed. A fabric switch has upstream ports associated with a serial link. A fabric controller is coupled to the switch. A host server includes a BIOS and a management controller. The host server has ports coupled to the serial link ports via cables to form lanes of the serial link. A memory is accessible by the controller and the management controller. The management controller reads an expected speed and width of the serial link from the memory. The BIOS determines an actual speed and width of the serial link. The management controller sends an error message if the actual speed and width do not match the expected speed and width.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: May 19, 2020
    Assignee: QUANTA COMPUTER INC.
    Inventors: Ching-Chih Shih, Lien-Hsun Chen, Chiao-Lun Tsai
  • Patent number: 10595444
    Abstract: A computing device for cooling an electronic component is provided. The computing device includes a chassis with a first end and a second end; fan modules located at the first end of the chassis; and a Peripheral Component Interconnect Express (PCIe) baseboard located at a front side of the chassis. The PCIe baseboard is configured to support placement thereof in the chassis in a first position and a second position. The second position of the PCIe baseboard is a 180-degree rotation from the first position. The PCIe baseboard includes GPU slots for installing a plurality of graphic processing units (GPUs), the GPUs including fan modules.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: March 17, 2020
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chiao-Lun Tsai, Hsin-Chieh Lin, Che-Wei Hsu
  • Publication number: 20200084919
    Abstract: A computing device for cooling an electronic component is provided. The computing device includes a chassis with a first end and a second end; fan modules located at the first end of the chassis; and a Peripheral Component Interconnect Express (PCIe) baseboard located at a front side of the chassis. The PCIe baseboard is configured to support placement thereof in the chassis in a first position and a second position. The second position of the PCIe baseboard is a 180-degree rotation from the first position. The PCIe baseboard includes GPU slots for installing a plurality of graphic processing units (GPUs), the GPUs including fan modules.
    Type: Application
    Filed: September 7, 2018
    Publication date: March 12, 2020
    Inventors: Chiao-Lun TSAI, Hsin-Chieh LIN, Che-Wei HSU
  • Publication number: 20190303315
    Abstract: A system and method for insuring efficiency of a serial link between a host server and a switch is disclosed. A fabric switch has upstream ports associated with a serial link. A fabric controller is coupled to the switch. A host server includes a BIOS and a management controller. The host server has ports coupled to the serial link ports via cables to form lanes of the serial link. A memory is accessible by the controller and the management controller. The management controller reads an expected speed and width of the serial link from the memory. The BIOS determines an actual speed and width of the serial link. The management controller sends an error message if the actual speed and width do not match the expected speed and width.
    Type: Application
    Filed: July 20, 2018
    Publication date: October 3, 2019
    Inventors: Ching-Chih SHIH, Lien-Hsun CHEN, Chiao-Lun TSAI
  • Publication number: 20110153902
    Abstract: A test interface card includes: a first specification bus adapted for coupling between a first specification interface controller of a device under test (DUT) and a signal converting interface card, and for transmitting a first test signal that is outputted by the first specification interface controller to the signal converting interface card for processing; a second specification bus adapted for coupling between the signal converting interface card and a storage module of the DUT, and for transmitting a processed signal that is outputted by the signal converting interface card as a result of processing the first test signal to the storage module; and a third specification bus adapted for forming a closed circuit with a second specification interface controller of the DUT, and for transmitting a second test signal that is outputted by the second specification interface controller back to the second specification interface controller.
    Type: Application
    Filed: September 16, 2010
    Publication date: June 23, 2011
    Applicant: Wistron Corporation
    Inventors: Chiao-Lun Tsai, Kuo-Hong Chuang