Abstract: A voltage meter includes a sampler, a gain circuit, an accumulator and a feedback circuit. The sampler samples an input signal to generate a series of first signals and a series of second signals. The gain circuit, coupled to the sampler, modifies at least one of the series of first signals and the series of second signals, to generate a series of modified first signals and a series of modified second signals. The accumulator, coupled to the gain circuit, accumulates an operational result of the series of modified first signals and the series of modified second signals, to generate an accumulation result. The feedback circuit, coupled between the accumulator and the sampler, sends a feedback signal back to the sampler according to the accumulation result.

Abstract: A transceiver and an operation method thereof are provided. The transceiver includes a transmitter and a receiver. The transmitter is configured to receive an output reference signal to provide an output signal to a signal channel. The receiver is coupled to the signal channel to receive a receiving reference signal to provide a receiving signal. The receiver includes a comparator unit and a signal adjusting unit. The comparator unit is configured to compare a first signal and a second signal to obtain the receiving signal. The signal adjusting unit is coupled between the output reference signal, the receiving reference signal and the comparator unit to adjust a voltage level of at least one of the output reference signal and the receiving reference signal to obtain the first signal and the second signal.

Abstract: An integrated circuit is provided. The integrated circuit includes a pad, a core circuit, an impedance matching component, a first switch and a second switch. The pad is configured to transmit a communication signal. A communication terminal of the core circuit is coupled to the pad, and a power terminal of the core circuit is coupled to a system voltage rail. A first terminal of the impedance matching component is coupled to the pad. A first terminal of the first switch is coupled to the system voltage rail, and a second terminal of the first switch is coupled to a second terminal of the impedance matching component. A first terminal of the second switch is coupled to a control terminal of the first switch, and a second terminal of the second switch is coupled to the second terminal of the impedance matching component.

Abstract: An integrated circuit is provided. The integrated circuit includes a pad, a core circuit, an impedance matching component, a first switch and a second switch. The pad is configured to transmit a communication signal. A communication terminal of the core circuit is coupled to the pad, and a power terminal of the core circuit is coupled to a system voltage rail. A first terminal of the impedance matching component is coupled to the pad. A first terminal of the first switch is coupled to the system voltage rail, and a second terminal of the first switch is coupled to a second terminal of the impedance matching component. A first terminal of the second switch is coupled to a control terminal of the first switch, and a second terminal of the second switch is coupled to the second terminal of the impedance matching component.

Abstract: A transceiver and an operation method thereof are provided. The transceiver includes a transmitter and a receiver. The transmitter is configured to receive an output reference signal to provide an output signal to a signal channel. The receiver is coupled to the signal channel to receive a receiving reference signal to provide a receiving signal. The receiver includes a comparator unit and a signal adjusting unit. The comparator unit is configured to compare a first signal and a second signal to obtain the receiving signal. The signal adjusting unit is coupled between the output reference signal, the receiving reference signal and the comparator unit to adjust a voltage level of at least one of the output reference signal and the receiving reference signal to obtain the first signal and the second signal.

Abstract: A differential signal transmission circuit including a pattern generator, a low voltage differential signal (LVDS) transmitter, a transition minimized differential signal (TMDS) receiver, and a comparator is provided. The pattern generator generates a plurality of test data. The LVDS transmitter is coupled to the pattern generator to receive the test data, and generates a test output signal according to the test data. The TMDS receiver receives a test input signal to output a plurality of decoded data. The comparator is coupled to the TMDS receiver to receive the decoded data and the pattern generator to receive the test data. The comparator compares the decoded data with the test data to output a test result of the TMDS receiver.

Abstract: A differential signal transmission circuit including a pattern generator, a low voltage differential signal (LVDS) transmitter, a transition minimized differential signal (TMDS) receiver, and a comparator is provided. The pattern generator generates a plurality of test data. The LVDS transmitter is coupled to the pattern generator to receive the test data, and generates a test output signal according to the test data. The TMDS receiver receives a test input signal to output a plurality of decoded data. The comparator is coupled to the TMDS receiver to receive the decoded data and the pattern generator to receive the test data. The comparator compares the decoded data with the test data to output a test result of the TMDS receiver.

Abstract: A switching control method capable of continuously providing power is utilized for a power supply system having a first power supply unit and a second power supply unit. The switching control method includes generating a first input signal and a second input signal; performing a logical operation process on the first input signal and the second input signal to generate a first control signal; delaying the second input signal for a delay time to generate a second control signal; controlling a coupling relationship between the first power supply unit and a load according to the first control signal; and controlling a coupling relationship between the second power supply unit and the load according to the second control signal.

Abstract: A method for detecting signals in a TMDS transmission system having a channel established between a receiver and a transmitter includes separating loadings of the receiver from the channel, providing a first reference current in a first differential line of the channel, providing a second reference current in a second differential line of the channel, computing a difference between the first reference current and a current provided by the transmitter via the first differential line to obtain a first current difference, computing a difference between the second reference current and a current provided by the transmitter via the second differential line to obtain a second current difference, and determining an operating state of the transmitter according to the first current difference and the second current difference.

Abstract: A delay lock loop (DLL) including a voltage control delay line (VCDL), a phase frequency detecting loop (PFD loop), and a phase limiting loop is provided. The VCDL generates an output clock signal according to a DC voltage signal, wherein the VCDL delays an input clock signal by a specific period so as to generate the output clock signal. The PFD loop generates the DC voltage signal according to the phase difference of the input clock signal and the output clock signal and is controlled by an initiation signal. The phase limiting loop limits the delay of the output clock signal to be less than a delay time and generates the initiation signal to enable the PFD loop. Furthermore, a clock signal generating method is also provided.

Abstract: A delay lock loop (DLL) including a voltage control delay line (VCDL), a phase frequency detecting loop (PFD loop), and a phase limiting loop is provided. The VCDL generates an output clock signal according to a DC voltage signal, wherein the VCDL delays an input clock signal by a specific period so as to generate the output clock signal. The PFD loop generates the DC voltage signal according to the phase difference of the input clock signal and the output clock signal and is controlled by an initiation signal. The phase limiting loop limits the delay of the output clock signal to be less than a delay time and generates the initiation signal to enable the PFD loop. Furthermore, a clock signal generating method is also provided.

Abstract: A dual-port input equalizer includes a control unit for generating a first control signal and a second control signal according to a selection signal, a first equalizer for receiving a first and second differential voltage for equalization according to the first control signal and the second control signal, which the first equalizer includes a first transistor, a second transistor, an passive loading portion, and a first zero-point generation circuit, a second equalizer for receiving a third and fourth differential voltage for equalization according to the first control signal and the second control signal, which the second equalizer includes a third transistor and a fourth transistor, which the drain of the first transistor, the second transistor, third transistor, and the fourth transistor coupled to the passive loading portion, and the source of the first transistor, the second transistor, third transistor, and the fourth transistor coupled to the first zero-point generation circuit.

Abstract: An impedance adjustment circuit for adjusting a terminal resistance includes a resistance evaluation unit and a terminal resistor unit. The resistance evaluation unit is utilized for evaluating a ratio of an off-chip resistor and a basic resistor to generate a control signal by a successive approximation method. The terminal resistor unit is coupled to the resistance evaluation unit, and is utilized for deciding a number of shunt basic resistors to provide a matched terminal resistance according to the control signal.

Abstract: A frequency dividing circuit performs a frequency dividing operation on N input clock signals to obtain N output clock signals, wherein N is a natural number greater than 1. The frequency dividing circuit includes a frequency divider and a flip-flop. The frequency divider samples an initial signal according to a first input clock signal of the N input clock signals to accordingly generate a first output clock signal of the N output clock signals. The initial signal corresponds with an inverse signal of the first output clock signal. The flip-flop samples the first output clock signal to accordingly generate a second output clock signal of the N output clock signals according to a second input clock signal of the N input clock signals.

Abstract: A dual-port input equalizer includes a control unit for generating a first control signal and a second control signal according to a selection signal, a first equalizer for receiving a first and second differential voltage for equalization according to the first control signal and the second control signal, which the first equalizer includes a first transistor, a second transistor, an passive loading portion, and a first zero-point generation circuit, a second equalizer for receiving a third and fourth differential voltage for equalization according to the first control signal and the second control signal, which the second equalizer includes a third transistor and a fourth transistor, which the drain of the first transistor, the second transistor, third transistor, and the fourth transistor coupled to the passive loading portion, and the source of the first transistor, the second transistor, third transistor, and the fourth transistor coupled to the first zero-point generation circuit.

Abstract: An impedance adjustment circuit for adjusting a terminal resistance includes a resistance evaluation unit and a terminal resistor unit. The resistance evaluation unit is utilized for evaluating a ratio of an off-chip resistor and a basic resistor to generate a control signal by a successive approximation method. The terminal resistor unit is coupled to the resistance evaluation unit, and is utilized for deciding a number of shunt basic resistors to provide a matched terminal resistance according to the control signal.

Abstract: A switching control method capable of continuously providing power is utilized for a power supply system having a first power supply unit and a second power supply unit. The switching control method includes generating a first input signal and a second input signal; performing a logical operation process on the first input signal and the second input signal to generate a first control signal; delaying the second input signal for a delay time to generate a second control signal; controlling a coupling relationship between the first power supply unit and a load according to the first control signal; and controlling a coupling relationship between the second power supply unit and the load according to the second control signal.

Abstract: A method for detecting signals in a TMDS transmission system is disclosed. A channel of the TMDS system is established between a receiver and a transmitter. The method includes separating loadings of the receiver from the channel, providing a first reference current in a first differential line of the channel, providing a second reference current in a second differential line of the channel, computing a difference between the first reference current and a current provided by the transmitter via the first differential line to obtain a first current difference, computing a difference between the second reference current and a current provided by the transmitter via the second differential line to obtain a second current difference, and determining an operating state of the transmitter according to the first current difference and the second current difference.

Abstract: A frequency dividing circuit performs a frequency dividing operation on N input clock signals to obtain N output clock signals, wherein N is a natural number greater than 1. The frequency dividing circuit includes a frequency divider and a flip-flop. The frequency divider samples an initial signal according to a first input clock signal of the N input clock signals to accordingly generate a first output clock signal of the N output clock signals. The initial signal corresponds with an inverse signal of the first output clock signal. The flip-flop samples the first output clock signal to accordingly generate a second output clock signal of the N output clock signals according to a second input clock signal of the N input clock signals.

Abstract: An apparatus for generating a spread spectrum clock with constant spread ratio includes a resistance-capacitance oscillator which is used for generating a first clock signal. In addition, the present invention further includes a spread spectrum charge pump circuit, a loop filter, and a voltage controlled oscillator (VCO). The spread spectrum charge pump circuit generates a spread spectrum current according to the first clock signal for changing/discharging the loop filter, so as to make the loop filter generate a control voltage. The VCO generates a control current and a spread spectrum clock signal according to the control voltage. The VCO feeds the control current back to the spread spectrum charge pump circuit to generate the spread spectrum current.