Abstract: Adaptive pulse generation circuits for clocking pulse latches with minimum hold time are provided. In one aspect, an adaptive pulse generation circuit employs a dynamic XOR-based logic gate configured to provide a pulse generation signal based on an XOR-based function of data input and data output-based signals of a pulse latch. A pull-down keeper circuit is configured to pull the pulse generation signal to a ground voltage in response to the pulse generation signal being in an inactive state while the clock signal is in an active state. A logic circuit is configured to generate an adaptive pulse signal to clock a pulse latch in response to the pulse generation signal and the clock signal being in an active state. This configuration results in the pulse width of the adaptive pulse signal corresponding to the input-to-output delay of the pulse latch.

Abstract: Middle-of-line (MOL) metal resistor temperature sensors for localized temperature sensing of active semiconductor areas in integrated circuits (ICs) are disclosed. One or more metal resistors are fabricated in a MOL layer in the IC adjacent to an active semiconductor area to sense ambient temperature in the adjacent active semiconductor area. Voltage of the metal resistor will change as a function of ambient temperature of the metal resistor, which can be sensed to measure the ambient temperature around devices in the active semiconductor layer adjacent to the metal resistor. By fabricating a metal resistor in the MOL layer, the metal resistor can be localized adjacent and close to semiconductor devices to more accurately sense ambient temperature of the semiconductor devices. The same fabrication processes used to create contacts in the MOL layer can be used to fabricate the metal resistor.

Abstract: A FinFET having a backgate and a barrier layer beneath the fin channel of the FinFET, where the barrier layer has a bandgap greater than that of the backgate. The barrier layer serves as an etch stop layer under the fin channel, resulting in reduced fin channel height variation. The backgate provides improved current control. There is less punchthrough due to the higher bandgap barrier layer. The FinFET may also include deeply embedded stressors adjacent to the source/drain diffusions through the high bandgap barrier layer.

Abstract: A local interconnect structure is provided that includes a gate-directed local interconnect coupled to an adjacent gate layer through a diffusion-directed local interconnect.