Patents by Inventor Chie-Chi Chen

Chie-Chi Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6911097
    Abstract: Provided is a process and apparatus characterized by a gas distribution plate in which a gas supply manifold directs gas bubbles from the bottom of a process tank upward and between wafers contained in a cassette and supported therewithin. This improved method and apparatus is used for effectively stripping photoresist from the larger semiconductor wafers having dense top conductive patterns with protuberant sidewalls. The method provides a scrubbing action that is parallel to the device array being formed on the wafer's surface. Broadly stated, the method of a chemical action on large substrates supported adjacent respective edge portions thereof in a carrier includes submerging the carrier and substrates supported thereby in a process tank containing a liquid chemical, and a gas distribution plate disposed on the bottom of the tank for directing gas bubbles upward and parallel to the surfaces of each substrate contained in the carrier to ensure that a uniform chemical action occurs.
    Type: Grant
    Filed: July 31, 2000
    Date of Patent: June 28, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chie-Chi Chen, Wen-Hsiang Tseng, Sheng-Liang Pan, Jen-Shiang Fang
  • Patent number: 6360756
    Abstract: A rinse tank for rinsing electronic substrates after a chemical process and a method for utilizing such rinse tank are provided. In the rinse tank, devices for performing a quick dump rinse; for performing a cascade overflow rinse and for feeding an inert gas bubbling are provided in the cavity of a single rinse tank. By utilizing the present invention novel rinse tank, the processing problems frequently observed in conventional rinse tanks where two rinse tanks are required for the quick dump rinse and for the cascade overflow rinse, such as particle re-deposition and a large floor space area requirement are eliminated. Furthermore, the wafer rinse process after a metal etching process can be accomplished in a total process time that is at least 2˜3 minutes shorter than that required by using conventional rinse tanks.
    Type: Grant
    Filed: June 3, 1999
    Date of Patent: March 26, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd
    Inventors: Chie-Chi Chen, Tzu-Yang Chung, Szu-Yao Wang, Sheng-Liang Pan
  • Patent number: 6281140
    Abstract: A process for reducing the surface roughness of a silicon dioxide gate insulator layer, that has been subjected to a boron ion implantation procedure, has been developed. The process features the use of an ammonium hydroxide-hydrogen peroxide solution, applied to the gate insulator layer, to reduce the surface roughness of the gate insulator layer, created by the boron ion implantation procedure. The treatment of the gate insulator layer, in the ammonium hydroxide-hydrogen peroxide solution, results in a surface roughness equivalent to the surface roughness of the gate insulator layer, prior to the boron ion implantation procedure.
    Type: Grant
    Filed: June 12, 2000
    Date of Patent: August 28, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chie-Chi Chen, Sheng-Liang Pan