Patents by Inventor Chie Hongo

Chie Hongo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160079473
    Abstract: A semiconductor light emitting element includes a first layer, a second layer, an intermediate layer, and a third layer. The first layer has a first surface having roughness including concave portions of which side surfaces are inclined and a second surface on an opposite side to the first surface. The first layer includes a first conductive-type first semiconductor layer. The second layer includes a second conductive-type second semiconductor layer. The intermediate layer is provided between the second surface and the second layer. The third layer is provided in the concave portions.
    Type: Application
    Filed: March 2, 2015
    Publication date: March 17, 2016
    Inventors: Rei HASHIMOTO, Kei KANEKO, Satoshi MITSUGI, Chie HONGO
  • Publication number: 20160079480
    Abstract: A semiconductor light-emitting device includes a first layer having a first surface and an opposing second surface. The first surface has a roughness including a bottom portion and a top portion. A light emitting layer is provided between the second surface and a second layer. An insulating layer is provided on the first surface. The insulating layer includes a first portion adjacent to the bottom portion and a second portion adjacent to the top portion along the first direction. The first portion has a thickness that is greater than a thickness of the second portion.
    Type: Application
    Filed: March 1, 2015
    Publication date: March 17, 2016
    Inventors: Kei KANEKO, Rei HASHIMOTO, Satoshi MITSUGI, Chie HONGO
  • Patent number: 9035336
    Abstract: A semiconductor device has an active layer, a first semiconductor layer of first conductive type, an overflow prevention layer disposed between the active layer and the first semiconductor layer, which is doped with impurities of first conductive type and which prevents overflow of electrons or holes, a second semiconductor layer of first conductive type disposed at least one of between the active layer and the overflow prevention layer and between the overflow prevention layer and the first semiconductor layer, and an impurity diffusion prevention layer disposed between the first semiconductor layer and the active layer, which has a band gap smaller than those of the overflow prevention layer, the first semiconductor layer and the second semiconductor layer and which prevents diffusion of impurities of first conductive type.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: May 19, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koichi Tachibana, Chie Hongo, Hajime Nago, Shinya Nunoue
  • Patent number: 8835950
    Abstract: A semiconductor device has an active layer, a first semiconductor layer of first conductive type, an overflow prevention layer disposed between the active layer and the first semiconductor layer, which is doped with impurities of first conductive type and which prevents overflow of electrons or holes, a second semiconductor layer of first conductive type disposed at least one of between the active layer and the overflow prevention layer and between the overflow prevention layer and the first semiconductor layer, and an impurity diffusion prevention layer disposed between the first semiconductor layer and the active layer, which has a band gap smaller than those of the overflow prevention layer, the first semiconductor layer and the second semiconductor layer and which prevents diffusion of impurities of first conductive type.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: September 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Tachibana, Chie Hongo, Hajime Nago, Shinya Nunoue
  • Publication number: 20140204970
    Abstract: A semiconductor device has an active layer, a first semiconductor layer of first conductive type, an overflow prevention layer disposed between the active layer and the first semiconductor layer, which is doped with impurities of first conductive type and which prevents overflow of electrons or holes, a second semiconductor layer of first conductive type disposed at least one of between the active layer and the overflow prevention layer and between the overflow prevention layer and the first semiconductor layer, and an impurity diffusion prevention layer disposed between the first semiconductor layer and the active layer, which has a band gap smaller than those of the overflow prevention layer, the first semiconductor layer and the second semiconductor layer and which prevents diffusion of impurities of first conductive type.
    Type: Application
    Filed: March 20, 2014
    Publication date: July 24, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Koichi TACHIBANA, Chie HONGO, Hajime NAGO, Shinya NUNOUE
  • Patent number: 8741686
    Abstract: A semiconductor device has an active layer, a first semiconductor layer of first conductive type, an overflow prevention layer disposed between the active layer and the first semiconductor layer, which is doped with impurities of first conductive type and which prevents overflow of electrons or holes, a second semiconductor layer of first conductive type disposed at least one of between the active layer and the overflow prevention layer and between the overflow prevention layer and the first semiconductor layer, and an impurity diffusion prevention layer disposed between the first semiconductor layer and the active layer, which has a band gap smaller than those of the overflow prevention layer, the first semiconductor layer and the second semiconductor layer and which prevents diffusion of impurities of first conductive type.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 3, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Tachibana, Chie Hongo, Hajime Nago, Shinya Nunoue
  • Patent number: 8466477
    Abstract: A semiconductor device has an active layer, a first semiconductor layer of first conductive type, an overflow prevention layer disposed between the active layer and the first semiconductor layer, which is doped with impurities of first conductive type and which prevents overflow of electrons or holes, a second semiconductor layer of first conductive type disposed at least one of between the active layer and the overflow prevention layer and between the overflow prevention layer and the first semiconductor layer, and an impurity diffusion prevention layer disposed between the first semiconductor layer and the active layer, which has a band gap smaller than those of the overflow prevention layer, the first semiconductor layer and the second semiconductor layer and which prevents diffusion of impurities of first conductive type.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: June 18, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Tachibana, Chie Hongo, Hajime Nago, Shinya Nunoue
  • Publication number: 20120138896
    Abstract: A semiconductor device has an active layer, a first semiconductor layer of first conductive type, an overflow prevention layer disposed between the active layer and the first semiconductor layer, which is doped with impurities of first conductive type and which prevents overflow of electrons or holes, a second semiconductor layer of first conductive type disposed at least one of between the active layer and the overflow prevention layer and between the overflow prevention layer and the first semiconductor layer, and an impurity diffusion prevention layer disposed between the first semiconductor layer and the active layer, which has a band gap smaller than those of the overflow prevention layer, the first semiconductor layer and the second semiconductor layer and which prevents diffusion of impurities of first conductive type.
    Type: Application
    Filed: February 16, 2012
    Publication date: June 7, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Koichi TACHIBANA, Chie HONGO, Hajime NAGO, Shinya NUNOUE
  • Publication number: 20120138895
    Abstract: A semiconductor device has an active layer, a first semiconductor layer of first conductive type, an overflow prevention layer disposed between the active layer and the first semiconductor layer, which is doped with impurities of first conductive type and which prevents overflow of electrons or holes, a second semiconductor layer of first conductive type disposed at least one of between the active layer and the overflow prevention layer and between the overflow prevention layer and the first semiconductor layer, and an impurity diffusion prevention layer disposed between the first semiconductor layer and the active layer, which has a band gap smaller than those of the overflow prevention layer, the first semiconductor layer and the second semiconductor layer and which prevents diffusion of impurities of first conductive type.
    Type: Application
    Filed: February 16, 2012
    Publication date: June 7, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Koichi TACHIBANA, Chie Hongo, Hajime Nago, Shinya Nunoue
  • Patent number: 7714350
    Abstract: A gallium nitride based semiconductor device comprises: a first gallium nitride based semiconductor film doped with magnesium; and a second gallium nitride based semiconductor film provided on the first gallium nitride based semiconductor film and doped with magnesium. The first gallium nitride based semiconductor film has substantially flat distributions of magnesium concentration and hydrogen atom concentration, and the magnesium concentration is higher than the hydrogen atom concentration. The second gallium nitride based semiconductor film has a first region in which the magnesium concentration decreases and the hydrogen atom concentration increases toward the surface, and the magnesium concentration in the first region is higher than the hydrogen atom concentration in the first region and higher than the magnesium concentration in the first gallium nitride based semiconductor film.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: May 11, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideto Sugawara, Chie Hongo
  • Publication number: 20100102296
    Abstract: A semiconductor device has an active layer, a first semiconductor layer of first conductive type, an overflow prevention layer disposed between the active layer and the first semiconductor layer, which is doped with impurities of first conductive type and which prevents overflow of electrons or holes, a second semiconductor layer of first conductive type disposed at least one of between the active layer and the overflow prevention layer and between the overflow prevention layer and the first semiconductor layer, and an impurity diffusion prevention layer disposed between the first semiconductor layer and the active layer, which has a band gap smaller than those of the overflow prevention layer, the first semiconductor layer and the second semiconductor layer and which prevents diffusion of impurities of first conductive type.
    Type: Application
    Filed: January 6, 2010
    Publication date: April 29, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Koichi TACHIBANA, Chie HONGO, Hajime NAGO, Shinya NUNOUE
  • Patent number: 7683390
    Abstract: A semiconductor device has an active layer, a first semiconductor layer of first conductive type, an overflow prevention layer disposed between the active layer and the first semiconductor layer, which is doped with impurities of first conductive type and which prevents overflow of electrons or holes, a second semiconductor layer of first conductive type disposed at least one of between the active layer and the overflow prevention layer and between the overflow prevention layer and the first semiconductor layer, and an impurity diffusion prevention layer disposed between the first semiconductor layer and the active layer, which has a band gap smaller than those of the overflow prevention layer, the first semiconductor layer and the second semiconductor layer and which prevents diffusion of impurities of first conductive type.
    Type: Grant
    Filed: February 25, 2008
    Date of Patent: March 23, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Tachibana, Chie Hongo, Hajime Nago, Shinya Nunoue
  • Patent number: 7531397
    Abstract: A semiconductor substrate encompasses a GaN substrate and a single-crystal layer formed of III-V nitride compound semiconductor epitaxially grown on the GaN substrate. The GaN substrate has a surface orientation defined by an absolute value of an off-angle of the surface from {0001} plane towards <1-100> direction lying in a range of 0.12 degree to 0.35 degree and by an absolute value of an off-angle of the surface from {0001} plane towards <11-20> direction lying in a range of 0.00 degree to 0.06 degree.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: May 12, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Tachibana, Chie Hongo, Shinya Nunoue, Masaaki Onomura
  • Patent number: 7397069
    Abstract: A semiconductor device has an active layer, a first semiconductor layer of first conductive type, an overflow prevention layer disposed between the active layer and the first semiconductor layer, which is doped with impurities of first conductive type and which prevents overflow of electrons or holes, a second semiconductor layer of first conductive type disposed at least one of between the active layer and the overflow prevention layer and between the overflow prevention layer and the first semiconductor layer, and an impurity diffusion prevention layer disposed between the first semiconductor layer and the active layer, which has a band gap smaller than those of the overflow prevention layer, the first semiconductor layer and the second semiconductor layer and which prevents diffusion of impurities of first conductive type.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: July 8, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Tachibana, Chie Hongo, Hajime Nago, Shinya Nunoue
  • Publication number: 20080151957
    Abstract: A semiconductor device has an active layer, a first semiconductor layer of first conductive type, an overflow prevention layer disposed between the active layer and the first semiconductor layer, which is doped with impurities of first conductive type and which prevents overflow of electrons or holes, a second semiconductor layer of first conductive type disposed at least one of between the active layer and the overflow prevention layer and between the overflow prevention layer and the first semiconductor layer, and an impurity diffusion prevention layer disposed between the first semiconductor layer and the active layer, which has a band gap smaller than those of the overflow prevention layer, the first semiconductor layer and the second semiconductor layer and which prevents diffusion of impurities of first conductive type.
    Type: Application
    Filed: February 25, 2008
    Publication date: June 26, 2008
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Koichi Tachibana, Chie Hongo, Hajime Nago, Shinya Nunoue
  • Publication number: 20080113497
    Abstract: A semiconductor substrate encompasses a GaN substrate and a single-crystal layer formed of III-V nitride compound semiconductor epitaxially grown on the GaN substrate. The GaN substrate has a surface orientation defined by an absolute value of an off-angle of the surface from {0001} plane towards <1-100> direction lying in a range of 0.12 degree to 0.35 degree and by an absolute value of an off-angle of the surface from {0001} plane towards <11-20> direction lying in a range of 0.00 degree to 0.06 degree.
    Type: Application
    Filed: January 3, 2008
    Publication date: May 15, 2008
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Koichi TACHIBANA, Chie Hongo, Shinya Nunoue, Masaaki Onomura
  • Patent number: 7339255
    Abstract: A semiconductor substrate encompasses a GaN substrate and a single-crystal layer formed of III-V nitride compound semiconductor epitaxially grown on the GaN substrate. The GaN substrate has a surface orientation defined by an absolute value of an off-angle of the surface from {0001} plane towards <1?100> direction lying in a range of 0.12 degree to 0.35 degree and by an absolute value of an off-angle of the surface from {0001} plane towards <11?20> direction lying in a range of 0.00 degree to 0.06 degree.
    Type: Grant
    Filed: July 21, 2005
    Date of Patent: March 4, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Tachibana, Chie Hongo, Shinya Nunoue, Masaaki Onomura
  • Patent number: 7333523
    Abstract: A semiconductor laser device comprising: a first cladding layer of a first conductivity type; an active layer provided on the first cladding layer and having a quantum well structure; an overflow blocking layer of a second conductivity type provided on the overflow blocking layer. The active layer includes a region having an impurity concentration is 3×1017 cm?3 or more and having a thickness of 30 nm or less between the overflow blocking layer and a well layer in the active layer closet to the overflow blocking layer.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: February 19, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Tanaka, Hideto Sugawara, Chie Hongo, Yoshiyuki Harada, Masaaki Onomura
  • Publication number: 20070096142
    Abstract: A semiconductor device has an active layer, a first semiconductor layer of first conductive type, an overflow prevention layer disposed between the active layer and the first semiconductor layer, which is doped with impurities of first conductive type and which prevents overflow of electrons or holes, a second semiconductor layer of first conductive type disposed at least one of between the active layer and the overflow prevention layer and between the overflow prevention layer and the first semiconductor layer, and an impurity diffusion prevention layer disposed between the first semiconductor layer and the active layer, which has a band gap smaller than those of the overflow prevention layer, the first semiconductor layer and the second semiconductor layer and which prevents diffusion of impurities of first conductive type.
    Type: Application
    Filed: August 29, 2006
    Publication date: May 3, 2007
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Koichi Tachibana, Chie Hongo, Hajime Nago, Shinya Nunoue
  • Publication number: 20070086496
    Abstract: A semiconductor light emitting device comprises: a first cladding layer made of nitride semiconductor of a first conductivity type; an active layer provided on the first cladding layer, the active layer including a first barrier layer made of nitride semiconductor, a second barrier layer made of nitride semiconductor, and a well layer made of nitride semiconductor, the well layer being provided between the first barrier layer and the second barrier layer; and a second cladding layer provided on the active layer, the second cladding layer being made of nitride semiconductor of a second conductivity type. The first and second barrier layers and the well layer contain indium. At least one of the first barrier layer and the second barrier layer has a thickness of 30 nm or more.
    Type: Application
    Filed: February 21, 2006
    Publication date: April 19, 2007
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Akira Tanaka, Chie Hongo, Yoshiyuki Harada, Hideto Sugawara, Masaaki Onomura, Hiroshi Katsuno