Patents by Inventor Chie Iwasa

Chie Iwasa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7464296
    Abstract: A failure candidates identifying system has a tree structure in which input patterns selected from a failure dictionary are set as nodes. The failure candidates identifying system comprises a failure candidates searching tree in which an input pattern does not exist with overlapping in a route from a root node of the nodes. A searching tree generating unit is configured to set as a child node of the node by selecting an input pattern of the smallest absolute value of a difference between a detect failure number at the observed failure mode and an un-detect failure number from the failure dictionary by observing a Detect failure or an un-detected failure at the input pattern of the node in case of the node has a child node.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: December 9, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Chie Iwasa
  • Publication number: 20050256655
    Abstract: A failure candidates identifying system has a tree structure in which input patterns selected from a failure dictionary are set as nodes. The failure candidates identifying system comprises a failure candidates searching tree in which an input pattern does not exist with overlapping in a route from a root node of the nodes. A searching tree generating unit is configured to set as a child node of the node by selecting an input pattern of the smallest absolute value of a difference between a detect failure number at the observed failure mode and an un-detect failure number from the failure dictionary by observing a Detect failure or an un-detected failure at the input pattern of the node in case of the node has a child node.
    Type: Application
    Filed: May 11, 2005
    Publication date: November 17, 2005
    Inventor: Chie Iwasa
  • Patent number: 6810344
    Abstract: In the present invention, plural test vectors are supplied to good and faulty samples as semiconductor devices in order to measure current values, and change rates of the current values corresponding to each test vector are calculated. The change rates of the current values in the good and faulty samples are then compared, and address pairs of test vectors to be used in a pass/fail decision for semiconductor devices are determined based on the comparison results. Test vectors to be used for performing an emission analysis are obtained based on the change rates of the current values obtained from the good and faulty samples. The obtained test vectors are supplied to the faulty sample in order to perform the emission analysis, in which emission patterns of the good and faulty samples are compared, by using an emission microscope, and a part of a defect in the faulty sample is detected.
    Type: Grant
    Filed: November 9, 2000
    Date of Patent: October 26, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Chie Iwasa