Patents by Inventor Chie Iwasaki

Chie Iwasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5623417
    Abstract: The functional design of logical circuits is represented using different types of functional components. The unification of the database and the interface permits the unification of functional design automation tools. These functional components are a data transfer component, an external pin component, a register component, a terminal component, a constant component, a function component, a memory component, a submodule component, a state machine component, and a logical expression component. An HDL (Hardware Description Language) file containing functional operation descriptions or functional design data is input, and the input functional data is assigned to each functional component stored in a functional component library through a functional component assignment process. The functional data records assigned by functional component are written into a function database by means of corresponding write sections provided in a functional data input interface.
    Type: Grant
    Filed: August 23, 1994
    Date of Patent: April 22, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Chie Iwasaki, Michiaki Muraoka
  • Patent number: 5062054
    Abstract: A printed circuit layout system using two or more of the following sub-systems: a pattern processing subsystem, a pattern design rule check subsystem, and a pattern connectivity verification characterizes any circuit pattern by a set of rectangles, each rectangle identified by a potential number and a layer, number and coordinates, and identifies terminals by potential number, layer number, and terminal names. The system eliminates the need to perform pattern OR processing and electrical connectivity search, as required by conventional schemes. The reforming and checking processes for the layout patterns are executed by a simple high speed method, making use of the features of the layout data. The system includes efficient methods for notch elimination, design rule checking, and connectivity checking.
    Type: Grant
    Filed: March 10, 1989
    Date of Patent: October 29, 1991
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshiyuki Kawakami, Masahiro Fukui, Ichiro Shigemoto, Chie Iwasaki