Patents by Inventor Chie Morii

Chie Morii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7759222
    Abstract: A method for fabricating a solid-state imaging device comprises: a step of forming a photodiode protection insulation film 6a; a step of forming a dummy protection insulation film 6c corresponding to the photodiode protection insulation film 6a both in the peripheral circuit region 1b and the scribe lane region 1c; and a step of forming an interlayer insulation film 9 for covering all three regions of a pixel region 1a in which pixels and the photodiode protection insulation film 6a are formed, a peripheral circuit region 1b in which a driving circuit and the dummy protection insulation film 6c are formed, and a scribe lane region 1c in which the dummy protection insulation film 6c is formed, wherein the dummy protection insulation film 6c causes an average height of a surface of the interlayer insulation film 9 included in each of the peripheral circuit region 1b and the scribe lane region 1c to be close to an average height of a surface of the interlayer insulation film 9 included in the pixel region 1a, be
    Type: Grant
    Filed: October 4, 2007
    Date of Patent: July 20, 2010
    Assignee: Panasonic Corporation
    Inventors: Chie Morii, Sougo Ohta
  • Publication number: 20080087976
    Abstract: A method for fabricating a solid-state imaging device comprises: a step of forming a photodiode protection insulation film 6a; a step of forming a dummy protection insulation film 6c corresponding to the photodiode protection insulation film 6a both in the peripheral circuit region 1b and the scribe lane region 1c; and a step of forming an interlayer insulation film 9 for covering all three regions of a pixel region 1a in which pixels and the photodiode protection insulation film 6a are formed, a peripheral circuit region 1b in which a driving circuit and the dummy protection insulation film 6c are formed, and a scribe lane region 1c in which the dummy protection insulation film 6c is formed, wherein the dummy protection insulation film 6c causes an average height of a surface of the interlayer insulation film 9 included in each of the peripheral circuit region 1b and the scribe lane region 1c to be close to an average height of a surface of the interlayer insulation film 9 included in the pixel region 1a, be
    Type: Application
    Filed: October 4, 2007
    Publication date: April 17, 2008
    Inventors: Chie Morii, Sougo Ohta