Abstract: An artificial random-number pattern generating circuit has a plurality of flip-flops each having a set signal input terminal and a clock signal input terminal; a plurality of selectors each of which forwards its output to the corresponding flip-flop and receives a first operation mode signal and/or a second operation mode signal; and an exclusive logical OR gate. The artificial random-number pattern generating circuit functions in three different ways, that is, as an artificial random-number pattern generator, a boundary scanning buffer or an input buffer, in accordance with the combinations of the first and second operation mode signals. The circuit can make not only a diagnosis of failure in the internal circuit of the large-scale integration (LSI) but also overall tests including those for input and output buffer circuits of the mounted LSI chip on a board or those for external wirings for the LSI.

Abstract: In a pseudo random pattern generation circuit having a normal input operation mode, a boundary scanning operation mode and an inherent pseudo random pattern generation mode, output stage selectors are provided to supply input data as output data without modification in the normal input operation mode. In addition, flipflops are provided to hold the data in the boundary scanning operation mode, so that the data held in the flipflops are not supplied as output signals. Thus, in the normal input operation mode, the data processing speed is increased, and in the boundary scanning operation mode, the data just before the boundary scanning operation mode is maintained without being outputted to an internal circuit of the LSI chip.