Abstract: A substrate structure for an image sensor package includes a bottom base and a frame layer. The bottom base has an upper surface formed with a plurality of first electrodes, and a lower surface formed with a plurality of second electrodes. An insulation layer is coated between the first electrodes and in direct surface contact with the upper surface of the bottom base. A frame layer is arranged on and in direct surface contact with the first electrodes and the insulation layer to form a cavity together with the bottom base. The insulation layer is interposed between the bottom base and the frame layer.

Abstract: A substrate structure for an image sensor package, the substrate structure includes a bottom base and a frame layer. The bottom base has an upper surface formed with a plurality of first electrodes, and a lower surface formed with a plurality of second electrodes, an insulation layer is coated between each of the first electrode, so as to the upper surface of the bottom base is smooth. A frame layer is arranged on the upper surface of the bottom base to form a cavity together with the bottom base.

Abstract: A jig structure for manufacturing an image sensor, the image sensor includes a substrate and a frame layer, wherein the jig is located on the substrate, then fill the filler in the jig to form the frame layer, the jig comprising a plurality of connection channel to produce a plurality of square shape, dummy channel, and at least a inlet connected the channel and the dummy channel, so that fill the filler into the channel to form the frame layer of the image sensor.

Abstract: A memory module structure of the invention is used for being assembled on a locking device. The memory module includes a substrate and a plurality of memories. The substrate has certain long sides and short sides. Notches are formed on the short sides for being secured by the locking device. Each of the plurality of memories has a suitable length and width. Some memories of the plurality of memories are transversely mounted on the substrate with respect to the substrate. The other memories of the plurality of memories are longitudinally mounted on the substrate with respect to the substrate. According to this structure, it is possible to suitably arrange a plurality of memories on the substrate so as to increase the memory capacity of the memory module.

Abstract: A jig structure for an integrated circuit package. The jig structure is used for integrated circuits to be covered by glue. The jig structure includes a base formed with a plurality of receiving regions for receiving the integrated circuits, a mold plate covering the base, a plurality of glue inlets formed on the mold plate at locations corresponding to each receiving region on the base, and a projection arranged between each glue inlet and its corresponding receiving region. The projection blocks and buffers the glue entering the receiving regions from the glue inlets. According to the jig structure, the mold flow of the glue can be effectively buffered when the glue is poured. Thus, it is not necessary to redesign the jig with the change of the relative position relationships between the glue inlets and the integrated circuits. The jig of this invention can be widely used for packaging various integrated circuits having different sizes and specifications.

Abstract: A memory module structure of the invention is used for being assembled on a locking device. The memory module includes a substrate and a plurality of memories. The substrate has certain long sides and short sides. Notches are formed on the short sides for being secured by the locking device. Each of the plurality of memories has a suitable length and width. Some memories of the plurality of memories are transversely mounted on the substrate with respect to the substrate. The other memories of the plurality of memories are longitudinally mounted on the substrate with respect to the substrate. According to this structure, it is possible to suitably arrange a plurality of memories on the substrate so as to increase the memory capacity of the memory module.

Abstract: The present invention provides a method of metal shadow-mask in process flow, which replaces the conventional photomask(s) and applies to the procedures of IC manufacturing to achieve the same efficiency as photomask(s). Additionally, the present invention can combine with photosensitive resist defined pattern to lessen a number of photomask(s) and complex procedures in IC manufacturing, especial in SOC, as well as decrease the cost of mask(s).

Abstract: The present invention provides a method of ceramic shadow-mask in process flow, which replaces the conventional photomask(s) and applies to the procedures of IC manufacturing to achieve the same efficiency as photomask(s). Additionally, the present invention can combine with photosensitive resist defined pattern to lessen a number of photomask(s) and complex procedures in IC manufacturing, especial in SOC, as well as decrease the cost of mask(s).

Abstract: A semiconductor package structure having central leads according to the invention includes a substrate, a semiconductor device, a plurality of wires, and glue. A long slot penetrating through the substrate is formed in the substrate. A plurality of bonding pads formed on the semiconductor device are mounted on substrate. The plurality of bonding pads on the semiconductor device are exposed via the long slot of the substrate. The length of the semiconductor device is smaller than that of the long slot of the substrate so that a channel is formed at one side of the long slot when the semiconductor device is mounted on the substrate. The plurality of wires are arranged within the long slot of the substrate for electrically connecting the plurality of bonding pads on the semiconductor device to the plurality of signal output terminals on the substrate. The glue is provided for sealing the upper surface of the substrate to protect the semiconductor device.

Abstract: A structure of stacked integrated circuits arranged on a circuit board includes a substrate, a lower integrated circuit, a plurality of wirings, a passivation layer, and an upper integrated circuit. The substrate has a first surface formed with signal input terminals, and a second surface formed with signal output terminals for electrically connecting to the circuit board. The lower integrated circuit has a first surface and a second surface. The first surface of the lower integrated circuit is adhered onto the first surface of the substrate. The second surface of the lower integrated circuit is formed with a plurality of bonding pads. The wirings each includes a first end and a second end opposite to the first end. The first ends of the wirings are electrically connected to the bonding pads of the lower integrated circuit, and the second ends of the wirings are electrically connected to the signal input terminals of the substrate, respectively.

Abstract: A structure of stacked integrated circuits for mounting on a circuit board includes a substrate, a lower integrated circuit, a plurality of wirings, a plurality of metallic balls, and an upper integrated circuit. The substrate has a first surface formed with signal input terminals and a second surface formed with signal output terminals for electrically connecting to the circuit board. The lower integrated circuit has a first surface adhered to the first surface of the substrate and a second surface formed with a plurality of bonding pads. Each of the wirings has a first end and a second end away from the first end. The first ends are electrically connected to the bonding pads of the lower integrated circuit. The second ends are electrically connected to the signal input terminals on the first surface of the substrate. The plurality of metallic balls are formed on the second surface of the lower integrated circuit.