Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes an optical interposer having optical waveguides; a plurality of chip stacks disposed over the optical interposer, each of the plurality of chip stacks including a first photonic IC chip and a memory chip over the first photonic IC chip; and a plurality of first laser source chips disposed adjacent to the plurality of chip stacks, respectively, wherein the optical waveguides in the optical interposer are configured as an optical interconnect structure to couple with the memory chip through the first photonic IC chip.

Abstract: A method of fabricating a semiconductor device includes forming at least one fin on a substrate, a plurality of dummy gates over the at least one fin, and a sidewall spacer on the dummy gates. Source and drain regions are epitaxially formed contacting the at least one fin and laterally adjacent the dummy gates, where forming the source and drain regions leaves a void below the source and drain regions and adjacent the dummy gates. The dummy gates are replaced with active gates, each having a gate dielectric on the sidewall spacer and a gate electrode on the gate dielectric. A patterned layer is formed exposing a selected active gate of the active gates. A first etch is performed to remove exposed portions of the gate electrode of the selected active gate. A second etch is performed, after the first etch, to remove exposed portions of a gate dielectric of the selected active gate.

Abstract: A plurality of processor dies may be attached to an interposer structure including interposer dielectric material layers having formed therein interposer metal interconnect structures, A dielectric matrix may be formed around the plurality of processor dies over the interposer structure. A router die may be attached to the plurality of processor dies. The router die includes router dielectric material layers having formed therein router metal interconnect structures and a router substrate having formed therein router through-substrate via structures therein. A backside of the router substrate may be thinned to expose end surfaces of the router through-substrate via structures. Memory dies may be attached to the router substrate after thinning the backside of the router substrate. Bonding pads of the memory dies are electrically connected to the router through-substrate via structures.

Abstract: An organic light-emitting diode (OLED) display may have an array of organic light-emitting diode pixels that each have OLED layers interposed between a cathode and an anode. Voltage may be applied to the anode of each pixel to control the magnitude of emitted light. The conductivity of the OLED layers may allow leakage current to pass between neighboring anodes in the display. To reduce leakage current and the accompanying cross-talk, the display may include active and/or passive leakage-mitigating structures. The passive leakage-mitigating structures may have an undercut that causes discontinuities in the overlying OLED layers. Active leakage-mitigating structures may include a conductive layer (e.g., a conductive ring) that drains leakage current to ground. Alternatively, the active leakage-mitigating structures may include a gate electrode modulator with a variable voltage that stops the current flow laterally.

Abstract: A method for manufacturing an implantable micro-biosensor includes the steps of: a) providing a substrate, b) forming on a first surface of the substrate a first working electrode which at least includes a first sensing section including a first conductive material, c) forming on the first surface of the substrate at least one second working electrode which at least includes a second sensing section disposed proximate to at least one side of the first sensing section, and d) forming a chemical reagent layer which at least covers the first conductive material of the first sensing section and which reacts with the analyte to produce a product.

Abstract: A method of forming a semiconductor device includes surrounding a dummy gate disposed over a fin with a dielectric material; forming a gate trench in the dielectric material by removing the dummy gate and by removing upper portions of a first gate spacer disposed along sidewalls of the dummy gate, the gate trench comprising a lower trench between remaining lower portions of the first gate spacer and comprising an upper trench above the lower trench; forming a gate dielectric layer, a work function layer and a glue layer successively in the gate trench; removing the glue layer and the work function layer from the upper trench; filling the gate trench with a gate electrode material after the removing; and removing the gate electrode material from the upper trench, remaining portions of the gate electrode material forming a gate electrode.

Abstract: A memory circuit includes a first memory array comprising a plurality of first memory cells, the plurality of first memory cells configured to store a first data element; a second memory array comprising a plurality of second memory cells, the plurality of second memory cells configured to store a second data element; and a control circuit operatively coupled to both of the first memory array and the second memory array, and configured to provide a multiply-accumulate (MAC) value at least based on simultaneously multiplying a third data element by the first data element and multiplying the third data element by the second data element.

Abstract: Provided is a biocompatible composition includes a chitosan-based hydrogel and a dextran solution. Also provided is a method for preparing the biocompatible composition includes reacting the chitosan-based hydrogel with the dextran solution via a cross-linking reaction. Further provided is a method of tissue adhesion includes administering the biocompatible composition to a subject in need thereof.

Abstract: A server comprising a circuitry, wherein the circuitry is configured to perform: generating an emulator in response to a request from a first user terminal of a first user; launching an application via the emulator; receiving streaming data and interaction data via the application; rendering the streaming data with the interaction data; recording the rendered streaming data and interaction data as a clip; and storing the clip for access from the first user terminal of the first user. According to the present disclosure, the clips may be generated in a more efficient and accurate manner, and a more immersive experience on watching the clips may be provided. Moreover, the review and share of clips may be more flexible. Therefore, the user experience may be improved.

Abstract: An insertion device includes an upper casing, a lower casing and an insertion module. When the lower casing is coupled to the upper casing, an abutment portion of the lower casing limits movement of a casing engaging structure of the upper casing, such that the upper casing cannot move downwardly so as to prevent unintentional insertion operation of the insertion device.

Abstract: An integrated fan-out (InFO) package includes a die, an encapsulant, and a horn antenna. The die has an active surface and a rear surface opposite to the active surface. The encapsulant laterally encapsulates the die. The horn antenna is electrically connected to the die. The horn antenna includes a top wall and a bottom wall respectively located on two opposite sides of the die and the encapsulant. A portion of the top wall is located within a span of the active surface of the die. A portion of the bottom wall is located within a span of the rear surface of the die.

Abstract: A method of manufacturing a structure having anodized parts includes: forming a bottom metal layer on a substrate; forming a top metal layer on the bottom metal layer; forming a mask layer on the top metal layer to expose a portion of a top surface of the top metal layer; etching the top metal layer through the mask layer until a top surface of the bottom metal layer is exposed, wherein an etch selectivity of the top metal layer and the bottom metal layer is greater than 2.0; anodizing the bottom metal layer through the mask layer to form an anodized segment; and removing the mask layer after the anodizing.

Abstract: A method of manufacturing a structure having anodized parts includes: forming a bottom metal pattern with a dielectric layer thereon on a substrate, in which the dielectric layer has an opening exposing the bottom metal pattern; forming a semiconductor layer to cover the dielectric layer; forming a first metal layer on the semiconductor layer; forming a second metal layer on the first metal layer; forming a mask layer on the second metal layer to expose a portion of a top surface of the second metal layer; etching the second metal layer through the mask layer until a top surface of the first metal layer is exposed, in which an etch selectivity of the second metal layer and the first metal layer is greater than 2.0; anodizing the first metal layer through the mask layer to form an anodized segment; and removing the mask layer.

Abstract: A method of forming an electrode with multi-dielectric layers includes: forming a metal pattern on a substrate, in which the metal pattern includes a first metal film on the substrate and a second metal film on a top surface of the first metal film, and the first and second metal films have different metal compositions; and anodizing the metal pattern in a liquid electrolyte to form a covering anodized portion which covers an unanodized portion, in which the covering anodized portion includes a sidewall oxide dielectric structure and a top oxide dielectric structure, the sidewall oxide dielectric structure is in contact with a side surface of the unanodized portion, the top oxide dielectric structure is in contact with top surfaces of the unanodized portion and the sidewall oxide dielectric structure, and the sidewall and top oxide dielectric structures have different effective permittivities.

Abstract: A method of manufacturing an electrode structure includes: etching the bottom metal layer through a first patterned photoresist including first and second mask portions to form a first metal pattern, a second metal pattern, and a bridge connected therebetween; removing the first mask portion; anodizing the bottom metal layer with the remained second mask portion by flowing an anodizing current from the first metal pattern; removing the remained second mask portion; depositing a conductive layer on the bottom metal layer to be in contact with an area of the second metal pattern that is unanodized; etching the conductive layer through a second patterned photoresist until an open segment of the bridge is exposed; and etching the open segment of the bridge through the second patterned photoresist until the bridge is electrically opened.

Abstract: A method of manufacturing a structure having an electrode and an anodized part includes: forming a top metal layer on a substrate; forming a top patterned photoresist on the top metal layer to expose a portion of a top surface of the top metal layer, in which the top patterned photoresist has a first mask portion and a second mask portion thicker than the first mask portion; anodizing the top metal layer through the top patterned photoresist to form an anodized segment; removing the first mask portion after the anodizing; and etching the top metal layer through the top patterned photoresist after the removing the first mask portion to form a top metal pattern.

Abstract: A method of manufacturing a structure having an electrode and an anodized part includes: forming a top metal layer on a substrate; forming a top patterned photoresist on the top metal layer to expose a portion of a top surface of the top metal layer, in which the top patterned photoresist has a first mask portion and a second mask portion thicker than the first mask portion; anodizing the top metal layer through the top patterned photoresist to form an anodized segment; removing the first mask portion after the anodizing; etching the top metal layer through the top patterned photoresist after the removing the first mask portion to form a top metal pattern; and reflowing the top patterned photoresist after the anodizing and before the etching.

Abstract: A method of manufacturing a structure having multi metal layers includes: depositing a top metal layer on a bottom metal layer; forming a patterned photoresist on the top metal layer; etching the top and bottom metal layers through first hollow portions of the patterned photoresist to respectively form a top metal pattern and a bottom metal pattern; forming a second hollow portion in the patterned photoresist to expose a portion of the top metal pattern; etching the top metal pattern through the second hollow portion until a top surface portion of the bottom metal pattern is exposed by the etched top metal pattern, in which an etch selectivity of the top and bottom metal layers in the etching the top metal pattern is greater than 1.0; and anodizing the top surface portion to form an anodized segment of the bottom metal layer.

Abstract: A method of manufacturing an interconnection structure includes: forming a first patterned photoresist on a bottom metal layer; etching the bottom metal layer to form first and second lower metal patterns; partially anodizing the etched bottom metal layer; removing the first patterned photoresist to expose a surface portion of the second lower metal pattern that is unanodized; depositing a conductive layer on the anodized bottom metal layer to be in contact with the surface portion; and etching the conductive layer through a second patterned photoresist to form a first upper conductive pattern that is above and electrically isolated from the first lower metal pattern and a second upper conductive pattern that is above the second lower metal pattern and in contact with the surface portion, in which the first and second upper conductive patterns entirely cover all non-insulated top surface of the anodized bottom metal layer.

Abstract: A method includes forming a reconstructed wafer, which includes forming a redistribution structure over a carrier, bonding a first plurality of memory dies over the redistribution structure, bonding a plurality of bridge dies over the redistribution structure, and bonding a plurality of logic dies over the first plurality of memory dies and the plurality of bridge dies. Each of the plurality of bridge dies interconnects, and is overlapped by corner regions of, four of the plurality of logic dies. A second plurality of memory dies are bonded over the plurality of logic dies. The plurality of logic dies form a first array, and the second plurality of memory dies form a second array.