Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a plurality of nanostructures over a substrate, and a gate electrode surrounding the nanostructures. The semiconductor device structure includes a source/drain (S/D) portion adjacent to the gate electrode, and an interlayer dielectric layer adjacent formed over the source/drain portion. The semiconductor device structure includes an etch stop layer adjacent between the source/drain portion and the interlayer dielectric layer, and a protective element adjacent formed over the interlayer dielectric layer.

Abstract: In a projection device and a light source system thereof, the light source system includes a light source module, a driver, and a control circuit. The light source module includes light sources to provide beams with different wavelength ranges. According to a selection signal, the control circuit selects one of a first pulse width modulation signal, a second pulse width modulation signal, and a third pulse width modulation signal as a pulse width modulation signal to output to the driver. The driver drives the light source corresponding to the selection signal with the pulse width modulation signal provided by the control circuit.

Abstract: An image capture device includes a casing, a camera module, a rotatable member, and a pan-tilt module. The casing includes front and rear casings. The camera module is disposed in the casing. A portion of the camera module is through an opening region of the front casing. The camera module includes a lens module bracket and a lens module disposed therein. The rotatable member is fixed on the lens module bracket. The rotatable member is configured to rotate the camera module when the rotatable member is rotated relative to the casing, so that the lens module is switched between horizontal and vertical shooting modes. The pan-tilt module includes a motor bracket, first and second motors. The first motor is connected between one end of the motor bracket and a sidewall of the casing. The second motor is connected to another end of the motor bracket.

Abstract: A heat dissipation structure including a circuit board, a heat component, a metal component, a heat dissipation medium, and a heat sink is proposed. The heat component is connected to one side of the circuit board. The metal component is connected to another side of the circuit board and has a first concave-convex surface. The heat dissipation medium is connected to the metal component. The heat sink is connected to the heat dissipation medium and has a second concave-convex surface. The heat component, the circuit board, the metal component, the heat dissipation medium, and the heat sink are connected in sequence. The shape of the first concave-convex surface corresponds to the shape of the second concave-convex surface. One side of the heat dissipation medium is connected to the first concave-convex surface, and another side of the heat dissipation medium is connected to the second concave-convex surface.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a semiconductor fin structure including first semiconductor layers and second semiconductor layers alternatingly stacked, laterally recessing the first semiconductor layers of the semiconductor fin structure to form first notches in the first semiconductor layers, forming first passivation layers on first sidewalls of the first semiconductor layers exposed from the first notches, and forming first inner spacer layers in the first notches.

Abstract: Semiconductor structures and methods of fabrication are provided. A method according to the present disclosure includes receiving a workpiece that includes an active region over a substrate and having first semiconductor layers interleaved by second semiconductor layers, and a dummy gate stack over a channel region of the active region, etching source/drain regions of the active region to form source/drain trenches that expose sidewalls of the active region, selectively and partially etching second semiconductor layers to form inner spacer recesses, forming inner spacer features in the inner spacer recesses, forming channel extension features on exposed sidewalls of the first semiconductor layers, forming source/drain features over the source/drain trenches, removing the dummy gate stack, selectively removing the second semiconductor layers to form nanostructures in the channel region, forming a gate structure to wrap around each of the nanostructures. The channel extension features include undoped silicon.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a number of channel members over a substrate, a gate structure wrapping around each of the number of channel members, a dielectric fin structure disposed adjacent to the gate structure, the dielectric fin structure includes a first dielectric layer disposed over the substrate and in direct contact with the first gate structure, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer. The third dielectric is disposed over the second dielectric layer and spaced apart from the first dielectric layer and the gate structure by the second dielectric layer. The dielectric fin structure also includes an isolation feature disposed directly over the third dielectric layer.

Abstract: A method for assessing acute kidney injury of inpatient includes the following steps. An electronic medical record data of an inpatient is captured by a processor, and the electronic medical record data includes a baseline basic serum creatinine concentration data. A target serum creatinine concentration data and a minimum post-admission serum creatinine concentration data of the inpatient are captured by the processor. A dynamic-increasing value of serum creatinine concentration is calculated to obtain by the processor based on the target serum creatinine concentration data, the baseline basic serum creatinine concentration data and the minimum post-admission serum creatinine concentration data. The dynamic-increasing value of serum creatinine concentration is analyzed by the processor to assess whether the inpatient is an inpatient suffering the acute kidney injury or not.

Abstract: An image capture device includes a casing, a camera module, a rotatable member, and a pan-tilt module. The casing includes front and rear casings. The camera module is disposed in the casing. A portion of the camera module is through an opening region of the front casing. The camera module includes a lens module bracket and a lens module disposed therein. The rotatable member is fixed on the lens module bracket. The rotatable member is configured to rotate the camera module when the rotatable member is rotated relative to the casing, so that the lens module is switched between horizontal and vertical shooting modes. The pan-tilt module includes a motor bracket, first and second motors. The first motor is connected between one end of the motor bracket and a sidewall of the casing. The second motor is connected to another end of the motor bracket.

Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.

Abstract: A pharmaceutical composition for promoting a cancer immunotherapy and a method for promoting a cancer immunotherapy are provided. The pharmaceutical composition includes an uncoupling protein 2 inhibitor and an interleukin-17 blockade. The method includes administering an effective concentration of a pharmaceutical composition to a subject in need thereof, in which the pharmaceutical composition includes an uncoupling protein 2 inhibitor and an interleukin-17 blockade.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a plurality of nanostructures over a substrate, and a gate electrode surrounding the nanostructures. The semiconductor device structure includes a source/drain portion adjacent to the gate electrode, and a semiconductor layer between the gate electrode and the source/drain portion.

Abstract: A semiconductor device includes semiconductor nanostructures disposed over a substrate, and an electrical isolation region comprising a void disposed over the substrate in a drain/source region. The semiconductor device further includes a source/drain epitaxial layer in contact with the semiconductor nanostructures and disposed over the electrical isolation region in the drain/source region. The source/drain epitaxial layer is disposed over the void. The semiconductor device further includes a gate dielectric layer disposed on and wrapped around each channel region of the semiconductor nanostructures, and a gate electrode layer disposed on the gate dielectric layer and wrapped around each channel region of the semiconductor nanostructures.

Abstract: A method according to the present disclosure includes providing a workpiece including a first fin-shaped structure and a second fin-shaped structure over a substrate, depositing a nitride liner over the substrate and sidewalls of the first fin-shaped structure and the second fin-shaped structure, forming an isolation feature over the nitride liner and between the first fin-shaped structure and the second fin-shaped structure, epitaxially growing a cap layer on exposed surfaces of the first fin-shaped structure and the second fin-shaped structure and above the nitride liner, crystalizing the cap layer, and forming a first source/drain feature over a first source/drain region of the first fin-shaped structure and a second source/drain feature over a second source/drain region of the second fin-shaped structure.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a number of channel members over a substrate, a gate structure wrapping around each of the number of channel members, a dielectric fin structure disposed adjacent to the gate structure, the dielectric fin structure includes a first dielectric layer disposed over the substrate and in direct contact with the first gate structure, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer. The third dielectric is disposed over the second dielectric layer and spaced apart from the first dielectric layer and the gate structure by the second dielectric layer. The dielectric fin structure also includes an isolation feature disposed directly over the third dielectric layer.

Abstract: The present disclosure provides embodiments of semiconductor devices. In one embodiment, the semiconductor device includes a dielectric layer and a fin-shaped structure disposed over the dielectric layer. The fin-shaped structure includes a first p-type doped region, a second p-type doped region, and a third p-type doped region, and a first n-type doped region, a second n-type doped region, and a third n-type doped region interleaving the first p-type doped region, the second p-type doped region, and the third p-type doped region. The first p-type doped region, the third p-type doped region and the third n-type doped region are electrically coupled to a first potential. The second p-type doped region, the first n-type doped region and the second n-type doped region are electrically coupled to a second potential different from the first potential.

Abstract: A method of fabricating a device includes providing a fin extending from a substrate, where the fin includes an epitaxial layer stack having a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes removing a portion of the epitaxial layer stack within a source/drain region of the semiconductor device to form a trench in the source/drain region that exposes lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers. After forming the trench, in some examples, the method further includes performing a dummy layer recess process to laterally etch ends of the plurality of dummy layers to form first recesses along a sidewall of the trench. In some embodiments, the method further includes conformally forming a cap layer along the exposed lateral surfaces of the plurality of semiconductor channel layers and within the first recesses.

Abstract: A memory array and a structure of the memory array are provided. The memory array includes flash transistors, word lines and bit lines. The flash transistors are arranged in columns and rows. The flash transistors in each column are in serial connection with one another. The word lines are respectively coupled to gate terminals of a row of the flash transistors. The bit lines are respectively coupled to opposite ends of a column of the flash transistors. Band-to-band tunneling current at a selected flash transistor is utilized as read current during a read operation. The BTB tunneling current flows from one of the source/drain terminals of the selected flash transistor to the substrate, rather than flowing from one of the source/drain terminals to the other. As a result, charges stored in multiple programming sites of each flash transistor can be respectively sensed.

Abstract: An optical component includes a phase diffraction grating and an amplitude diffraction grating. The phase diffraction grating includes a center concave section and a plurality of ring stages. The ring stages surround the center concave section. The center concave section and the ring stages form a cavity, where a light source is disposed in the cavity and emits the light to the optical component. Each of the ring stages has a stage surface. Each of the stage surfaces includes a plurality of ring microstructures arranged in concentric circles. The widths of each ring microstructure in at least one of the ring stages are less than the quarter wavelength of the light. The amplitude diffraction grating includes a center convex section and a plurality of ring parts. The center convex section and the center concave section are aligned. The ring parts surround the central convex section.

Abstract: A ring for clasping a cylindrical object includes a first element, a second element and a switch mechanism. The second element is circumferentially butted with the first element, and one end of the first element is adjacent to one end of the second element. The end of the second element has a protrusion protruding outwardly. The switch mechanism includes an abutting member adjacent to the end of the first element and configured to be rotated to abut against or move away from the protrusion of the end of the second element. When the abutting member is rotated and abuts against the protrusion of the end of the second element, the second element is fixed; when the abutting member is rotated and moves away from the protrusion of the end of the second element, the second element is released.