Patents by Inventor Chieh-Chen Fu

Chieh-Chen Fu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240038712
    Abstract: A semiconductor device package and a method of manufacturing a semiconductor device package are provided. The semiconductor device package includes a carrier, a first component, a second component, and a protective element. The first component and the second component are arranged side by side in a first direction over the carrier. The protective element is disposed over a top surface of the carrier and extending from space under the first component toward a space under the second component. The protective element includes a first portion and a second portion protruded oppositely from edges of the first component by different distances, and the first portion and the second portion are arranged in a second direction angled with the first direction.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 1, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jung Jui KANG, Shih-Yuan SUN, Chieh-Chen FU
  • Patent number: 11474301
    Abstract: A device is provided. The device may be an optical device, a light coupling device, or a tunable light coupling device. The device includes a first portion, a lens, a light emitting element, and a waveguide. The first portion is disposed adjacent to a surface of a substrate and has a first side and a second side opposite to the first side. The light emitting element is disposed adjacent to the second side of the first portion. The lens is disposed adjacent to the first side of the first portion and between the light emitting element and the waveguide.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: October 18, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chang-Feng You, Jr-Wei Lin, Chieh-Chen Fu, Kao-Ming Su, Chen Yuan Weng
  • Publication number: 20220214488
    Abstract: A device is provided. The device may be an optical device, a light coupling device, or a tunable light coupling device. The device includes a first portion, a lens, a light emitting element, and a waveguide. The first portion is disposed adjacent to a surface of a substrate and has a first side and a second side opposite to the first side. The light emitting element is disposed adjacent to the second side of the first portion. The lens is disposed adjacent to the first side of the first portion and between the light emitting element and the waveguide.
    Type: Application
    Filed: January 7, 2021
    Publication date: July 7, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chang-Feng YOU, Jr-Wei LIN, Chieh-Chen FU, Kao-Ming SU, Chen Yuan Weng
  • Patent number: 11329016
    Abstract: A semiconductor device package includes a carrier, an emitting device, a first building-up circuit and a first package body. The carrier has a first surface, a second surface opposite to the first surface and a lateral surface extending from the first surface to the second surface. The emitting element is disposed on the first surface of carrier. The first building-up circuit is disposed on the second surface of the carrier. The first package body encapsulates the lateral surface of the carrier.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: May 10, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Meng-Wei Hsieh, Chieh-Chen Fu
  • Publication number: 20210249369
    Abstract: A semiconductor device package includes a carrier, an emitting device, a first building-up circuit and a first package body. The carrier has a first surface, a second surface opposite to the first surface and a lateral surface extending from the first surface to the second surface. The emitting element is disposed on the first surface of carrier. The first building-up circuit is disposed on the second surface of the carrier. The first package body encapsulates the lateral surface of the carrier.
    Type: Application
    Filed: February 12, 2020
    Publication date: August 12, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Meng-Wei HSIEH, Chieh-Chen FU
  • Publication number: 20210167053
    Abstract: A semiconductor device package includes a first semiconductor device having a first surface, an interconnection element having a surface substantially coplanar with the first surface of the first semiconductor device, a first encapsulant encapsulating the first semiconductor device and the interconnection element, and a second semiconductor device disposed on and across the first semiconductor device and the interconnection element.
    Type: Application
    Filed: February 8, 2021
    Publication date: June 3, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chang-Yu LIN, Chi-Han CHEN, Chieh-Chen FU
  • Patent number: 10930627
    Abstract: A semiconductor device package includes a first semiconductor device having a first surface, an interconnection element having a surface substantially coplanar with the first surface of the first semiconductor device, a first encapsulant encapsulating the first semiconductor device and the interconnection element, and a second semiconductor device disposed on and across the first semiconductor device and the interconnection element.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: February 23, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chang-Yu Lin, Chi-Han Chen, Chieh-Chen Fu
  • Patent number: 10784208
    Abstract: The present disclosure provides a semiconductor package device and a method for manufacturing the same. In embodiments of the present disclosure, a semiconductor package device includes a carrier, a first antenna, a second antenna, a package body and a first shield. The carrier includes an antenna area and a component area. The first antenna is formed on the antenna area. The second antenna extends from the antenna area and over the first antenna. The second antenna is electrically connected to the first antenna. The package body includes a first portion covering the component area and a second portion covering the antenna area. The first shield is conformally formed on the first portion of the package body and exposes the second portion of package body.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: September 22, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Kuo-Hsien Liao, Cheng-Nan Lin, Chieh-Chen Fu
  • Publication number: 20200212023
    Abstract: A semiconductor device package includes a first semiconductor device having a first surface, an interconnection element having a surface substantially coplanar with the first surface of the first semiconductor device, a first encapsulant encapsulating the first semiconductor device and the interconnection element, and a second semiconductor device disposed on and across the first semiconductor device and the interconnection element.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chang-Yu LIN, Chi-Han CHEN, Chieh-Chen FU
  • Patent number: 10431554
    Abstract: A semiconductor device package includes: (1) a carrier; (2) an electronic component disposed over a top surface of the carrier; (3) a package body disposed over the top surface of the carrier and covering the electronic component; and (4) a shield layer, including a first magnetically permeable layer disposed over the package body, a first electrically conductive layer disposed over the first magnetically permeable layer, and a second magnetically permeable layer disposed over the first electrically conductive layer. The first electrically conductive layer is interposed between the first magnetically permeable layer and the second magnetically permeable layer. A permeability of the first electrically conductive layer is different from a permeability of the first magnetically permeable layer and a permeability of the second magnetically permeable layer.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: October 1, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: I-Chia Lin, Chieh-Chen Fu, Kuo Hsien Liao, Cheng-Nan Lin
  • Publication number: 20180158783
    Abstract: A semiconductor device package includes: (1) a carrier; (2) an electronic component disposed over a top surface of the carrier; (3) a package body disposed over the top surface of the carrier and covering the electronic component; and (4) a shield layer, including a first magnetically permeable layer disposed over the package body, a first electrically conductive layer disposed over the first magnetically permeable layer, and a second magnetically permeable layer disposed over the first electrically conductive layer. The first electrically conductive layer is interposed between the first magnetically permeable layer and the second magnetically permeable layer. A permeability of the first electrically conductive layer is different from a permeability of the first magnetically permeable layer and a permeability of the second magnetically permeable layer.
    Type: Application
    Filed: January 15, 2018
    Publication date: June 7, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: I-Chia LIN, Chieh-Chen FU, Kuo Hsien LIAO, Cheng-Nan LIN
  • Patent number: 9871005
    Abstract: A semiconductor device package includes a carrier, an electronic component disposed over a top surface of the carrier, and a package body disposed over the top surface of the carrier and covering the electronic component. The semiconductor device package further includes a shield layer, which in turn includes a first electrically conductive layer, a first magnetically permeable layer, and a second electrically conductive layer, where the first magnetically permeable layer is interposed between and directly contacts the first electrically conductive layer and the second electrically conductive layer.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: January 16, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: I-Chia Lin, Chieh-Chen Fu, Kuo Hsien Liao, Cheng-Nan Lin
  • Publication number: 20170200682
    Abstract: A semiconductor device package includes a carrier, an electronic component disposed over a top surface of the carrier, and a package body disposed over the top surface of the carrier and covering the electronic component. The semiconductor device package further includes a shield layer, which in turn includes a first electrically conductive layer, a first magnetically permeable layer, and a second electrically conductive layer, where the first magnetically permeable layer is interposed between and directly contacts the first electrically conductive layer and the second electrically conductive layer.
    Type: Application
    Filed: January 7, 2016
    Publication date: July 13, 2017
    Inventors: I-Chia LIN, Chieh-Chen FU, Kuo Hsien LIAO, Cheng-Nan LIN
  • Publication number: 20170077039
    Abstract: The present disclosure provides a semiconductor package device and a method for manufacturing the same. In embodiments of the present disclosure, a semiconductor package device includes a carrier, a first antenna, a second antenna, a package body and a first shield. The carrier includes an antenna area and a component area. The first antenna is formed on the antenna area. The second antenna extends from the antenna area and over the first antenna. The second antenna is electrically connected to the first antenna. The package body includes a first portion covering the component area and a second portion covering the antenna area. The first shield is conformally formed on the first portion of the package body and exposes the second portion of package body.
    Type: Application
    Filed: June 7, 2016
    Publication date: March 16, 2017
    Inventors: Kuo-Hsien Liao, Cheng-Nan Lin, Chieh-Chen Fu
  • Patent number: 9269673
    Abstract: A semiconductor device package includes a substrate, at least one component, a package body, a first conductive layer, a first shielding layer, a second shielding layer and a second conductive layer. The component is disposed on a first surface of the substrate. The package body is disposed on the first surface of the substrate and covers the component. The first conductive layer covers the package body and at least a portion of the substrate. The first shielding layer covers the first conductive layer and has a first thickness and includes a high conductivity material. The second shielding layer covers the first shielding layer and has a second thickness and includes a high permeability material. A ratio of the first thickness to the second thickness being in a range of 0.2 to 3. The second conductive layer covers the second shielding layer.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: February 23, 2016
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: I-Chia Lin, Chieh-Chen Fu, Kuo-Hsien Liao, Cheng-Nan Lin
  • Patent number: 8963316
    Abstract: The present invention relates to a semiconductor device and a method for making the same. The semiconductor device includes a substrate, a first redistribution layer and a conductive via. The substrate has a substrate body and a pad. The pad and the first redistribution layer are disposed adjacent to the first surface of the substrate body, and electrically connected to each other. The interconnection metal is disposed in a through hole of the substrate body, and contacts the first redistribution layer. Whereby, the pad can be electrically connected to the second surface of the substrate body through the first redistribution layer and the conductive via.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: February 24, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chih-Jing Hsu, Ying-Te Ou, Chieh-Chen Fu, Che-Hau Huang
  • Publication number: 20130207260
    Abstract: The present invention relates to a semiconductor device and a method for making the same. The semiconductor device includes a substrate, a first redistribution layer and a conductive via. The substrate has a substrate body and a pad. The pad and the first redistribution layer are disposed adjacent to the first surface of the substrate body, and electrically connected to each other. The interconnection metal is disposed in a through hole of the substrate body, and contacts the first redistribution layer. Whereby, the pad can be electrically connected to the second surface of the substrate body through the first redistribution layer and the conductive via.
    Type: Application
    Filed: February 15, 2012
    Publication date: August 15, 2013
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chih-Jing Hsu, Ying-Te Ou, Chieh-Chen Fu, Che-Hau Huang
  • Patent number: 8120148
    Abstract: A package structure with an embedded die includes a core layer, a first build-up wiring structure, and a second build-up wiring structure. The core layer has a first surface and a second surface opposite thereto. Besides, the core layer includes a first dielectric layer, a leadframe, a die, a first signal layer, and a second signal layer. The die is disposed on and electrically connected to the leadframe. The die and the leadframe are embedded in the first dielectric layer. The first signal layer is disposed on an upper surface of the first dielectric layer and electrically connected to the leadframe. The second signal layer is disposed on a bottom surface of the first dielectric layer and electrically connected to the leadframe. The first and the second build-up wiring structures are disposed on the first and the second surfaces of the core layer, respectively.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: February 21, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuo-Hua Chen, Ying-Te Ou, Chieh-Chen Fu
  • Publication number: 20110127654
    Abstract: A semiconductor package and manufacturing methods thereof are provided. In one embodiment, the semiconductor package includes a die, a shield, a package body, and a redistribution layer. The die has an active surface and an inactive surface. The shield is disposed over the inactive surface of the die. The package body encapsulates the die and a first portion of the shield, where a first surface of the package body is substantially coplanar with the active surface of the die. The redistribution layer is disposed on the active surface of the die and on portions of the first surface of the package body.
    Type: Application
    Filed: November 29, 2010
    Publication date: June 2, 2011
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC..,
    Inventors: Chaofu Weng, John Richard Hunt, Li Chuan Tsai, Yi Ting Wu, Chieh-Chen Fu, Ying-Te Ou
  • Publication number: 20100006330
    Abstract: A process of an embedded chip package structure includes following steps. Firstly, a metal core layer having a first surface, a second surface opposite to the first surface, an opening, and a number of through holes are provided. The opening and the through holes connect the first surface and the second surface. A chip is then disposed in the opening. Next, a dielectric layer is formed in the opening and the through holes to fix the chip in the opening. Thereafter, a number of conductive vias are respectively formed in the through holes and insulated from the metal core layer by a portion of the dielectric layer located in the through holes. A circuit structure is then formed on the first surface of the metal core layer by performing a build-up process, and the circuit structure electrically connects the chip and the conductive vias.
    Type: Application
    Filed: June 26, 2009
    Publication date: January 14, 2010
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chieh-Chen Fu, Ying-Te Ou, Yung-Hui Wang