Abstract: A method for performing a lithography process is provided. The method includes forming a photoresist layer over a substrate, providing a plurality of target droplets to a source vessel, and providing a plurality of first laser pulses according to a control signal provided by a controller to irradiate the target droplets in the source vessel to generate plasma as an EUV radiation. The plasma is generated when the control signal indicates a temperature of the source vessel is within a temperature threshold value. The method further includes directing the EUV radiation from the source vessel to the photoresist layer to form a patterned photoresist layer and developing and etching the patterned photoresist layer to form a circuit layout.

Abstract: A polysilicon well is formed at a cross-road portion between a plurality of pixel sensors in a pixel sensor array. Moreover, the underlying oxide layer between the polysilicon well and a semiconductor layer of the pixel sensor array may be thinner than other areas of the oxide layer. The polysilicon well and the thinner oxide layer may reduce the likelihood of and/or the magnitude of lateral etching that occurs during etching of the semiconductor layer to form recesses in which a BDTI structure of the pixel sensor array is formed. Moreover, the bottom of the BDTI structure being surrounded by the polysilicon well enables a voltage bias to be applied to the BDTI structure through the polysilicon well to passivate damage that might have occurred to the semiconductor layer around the bottom of the BDTI structure.

Abstract: A battery structure includes at least one electrode lamination layer, at least one first conductive member and at least one second conductive member. Each electrode lamination layer includes a plurality of first electrode layers, a plurality of second electrode layers and a plurality of insulating layers, wherein each insulating layer is disposed between any immediately-adjacent two of the first electrode layers and second electrode layers. The electrode lamination layer is disposed between the first conductive member and the second conductive member, wherein each first electrode layer or each second electrode layer is electrically connected with and substantially perpendicular to the first conductive member or the second conductive member.

Abstract: A torsion angle and rotation angle measurement device includes an input rotation disk, an output rotation disk, at least two torsion measuring modules and a rotation measuring module. The output rotation disk is coaxially and rotatably connected with the input rotation disk. At least two torsion measuring modules are disposed between the input rotation disk and the output rotation disk. Each torsion measuring module includes a rotary variable resistor and a torsion measuring arm. The rotary variable resistor is disposed on the output rotation disk. The torsion measuring arm is pivotally connected with the rotary variable resistor at a first end thereof, and is slidably connected with the input rotation disk at an second opposite end. When the input rotation disk rotates relative to the output rotation disk, the rotary variable resistor measures an angle indicating the input rotation disk rotating relative to the output rotation disk.

Abstract: A torsion angle and rotation angle measurement device includes an input rotation disk, an output rotation disk, at least two torsion measuring modules and a rotation measuring module. The output rotation disk is coaxially and rotatably connected with the input rotation disk. At least two torsion measuring modules are disposed between the input rotation disk and the output rotation disk. Each torsion measuring module includes a rotary variable resistor and a torsion measuring arm. The rotary variable resistor is disposed on the output rotation disk. The torsion measuring arm is pivotally connected with the rotary variable resistor at a first end thereof, and is slidably connected with the input rotation disk at an second opposite end. When the input rotation disk rotates relative to the output rotation disk, the rotary variable resistor measures an angle indicating the input rotation disk rotating relative to the output rotation disk.

Abstract: A battery structure includes at least one electrode lamination layer, at least one first conductive member and at least one second conductive member. Each electrode lamination layer includes a plurality of first electrode layers, a plurality of second electrode layers and a plurality of insulating layers, wherein each insulating layer is disposed between any immediately-adjacent two of the first electrode layers and second electrode layers. The electrode lamination layer is disposed between the first conductive member and the second conductive member, wherein each first electrode layer or each second electrode layer is electrically connected with and substantially perpendicular to the first conductive member or the second conductive member.

Abstract: For receiving an input data, a pattern data and a data clock signal and outputting a hit signal and an address signal, a content addressable memory includes a plurality of content addressable memory units connected in series, each content addressable memory unit being adapted to receive the input data and the data clock signal and to output a comparison result signal, and an encoder coupled to the comparison result signal of each content addressable memory unit and adapted for outputting a hit signal and a memory address signal subject to the comparison result signal received.

Abstract: For receiving an input data, a pattern data and a data clock signal and outputting a hit signal and an address signal, a content addressable memory is disclosed to include a plurality of content addressable memory units connected in series, each content addressable memory unit being adapted to receive the input data and the data clock signal and to output a comparison result signal, and an encoder coupled to the comparison result signal of each content addressable memory unit and adapted for outputting a hit signal and a memory address signal subject to the comparison result signal received.