Patents by Inventor Chieh Chih Huang

Chieh Chih Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250169146
    Abstract: A semiconductor device includes: a substrate; a channel layer disposed on the substrate; a barrier layer disposed on the channel layer; and a cap layer disposed on the barrier layer. The semiconductor device further includes: a gate electrode disposed on the barrier layer; a source electrode and a drain electrode disposed on the barrier layer and respectively at opposite sides of the gate electrode; a spike region formed below at least one of the source electrode and the drain electrode; and a passivation layer disposed on the barrier layer and extending onto sidewalls and top surfaces of the source electrode and the drain electrode. The spike region includes titanium nitride (TiN). The passivation layer is in contact with the cap layer.
    Type: Application
    Filed: January 17, 2025
    Publication date: May 22, 2025
    Inventors: Chieh-Chih HUANG, Yan-Cheng LIN, Cheng-Kuo LIN, Wei-Chou WANG, Che-Kai LIN, Jiun-De WU
  • Patent number: 12237382
    Abstract: A semiconductor device includes: a substrate; a channel layer disposed on the substrate, wherein the channel layer is made of GaN; a barrier layer disposed on the channel layer, wherein the barrier layer is made of AlzGa1-zN; and an inserting structure inserted between the channel layer and the barrier layer. The inserting structure includes: a first inserting layer disposed on the channel layer, wherein the first inserting layer is made of AlxGa1-xN; and a second inserting layer disposed on the first inserting layer, wherein the second inserting layer is made of AlyGa1-yN, and y is greater than x. The semiconductor device further includes: a gate electrode disposed on the barrier layer; a source electrode and a drain electrode disposed on the barrier layer and respectively at opposite sides of the gate electrode; and a spike region formed below at least one of the source electrode and the drain electrode.
    Type: Grant
    Filed: May 30, 2022
    Date of Patent: February 25, 2025
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Chieh-Chih Huang, Yan-Cheng Lin, Cheng-Kuo Lin, Wei-Chou Wang, Che-Kai Lin, Jiun-De Wu
  • Publication number: 20220406905
    Abstract: A semiconductor device includes: a substrate; a channel layer disposed on the substrate, wherein the channel layer is made of GaN; a barrier layer disposed on the channel layer, wherein the barrier layer is made of AlzGa1-zN; and an inserting structure inserted between the channel layer and the barrier layer. The inserting structure includes: a first inserting layer disposed on the channel layer, wherein the first inserting layer is made of AlxGa1-xN; and a second inserting layer disposed on the first inserting layer, wherein the second inserting layer is made of AlyGa1-yN, and y is greater than x. The semiconductor device further includes: a gate electrode disposed on the barrier layer; a source electrode and a drain electrode disposed on the barrier layer and respectively at opposite sides of the gate electrode; and a spike region formed below at least one of the source electrode and the drain electrode.
    Type: Application
    Filed: May 30, 2022
    Publication date: December 22, 2022
    Inventors: Chieh-Chih HUANG, Yan-Cheng LIN, Cheng-Kuo LIN, Wei-Chou WANG, Che-Kai LIN
  • Publication number: 20200303532
    Abstract: A GaN-based field effect transistor comprises a semiconductor substrate, an epitaxial structure formed on the semiconductor substrate, a source electrode, a drain electrode, and a gate electrode. The epitaxial structure comprises a buffer layer, a channel layer, a spacer layer, an n-type doped barrier layer, a barrier layer, and a capping layer, sequentially. The epitaxial structure has a source recess and a drain recess. A bottom of the source recess is defined by the n-type doped barrier layer or the spacer layer. A bottom of the drain recess is defined by the n-type doped barrier layer or the spacer layer. The source electrode is formed in the source recess. The drain electrode is formed in the drain recess. The gate electrode is formed on the capping layer between the source electrode and the drain electrode.
    Type: Application
    Filed: March 20, 2019
    Publication date: September 24, 2020
    Inventors: Che-Kai LIN, Chieh-Chih HUANG, Wei-Chou WANG, Walter Tony WOHLMUTH
  • Patent number: 9911611
    Abstract: A method of fabricating a semiconductor device includes forming a hard mask (HM) mandrel along a first direction over a material layer, forming a first spacer along a sidewall of the HM mandrel, forming a second spacer along a sidewall of the first spacer and forming a patterned photoresist layer having a first line opening over the HM mandrel, the first spacer and the second spacer. First portions of the HM mandrel, the first spacer and the second spacer are exposed within the first line opening. The method also includes removing the first portion of the first spacer through the first line opening to expose a first portion of the material layer and etching the exposed first portion of the material layer to form a first opening in the material layer by using the exposed first portions of the HM mandrel and the second spacer as a sub-etch-mask.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: March 6, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Sung Yen, Ru-Gun Liu, Chieh Chih Huang
  • Publication number: 20170271160
    Abstract: A method of fabricating a semiconductor device includes forming a hard mask (HM) mandrel along a first direction over a material layer, forming a first spacer along a sidewall of the HM mandrel, forming a second spacer along a sidewall of the first spacer and forming a patterned photoresist layer having a first line opening over the HM mandrel, the first spacer and the second spacer. First portions of the HM mandrel, the first spacer and the second spacer are exposed within the first line opening. The method also includes removing the first portion of the first spacer through the first line opening to expose a first portion of the material layer and etching the exposed first portion of the material layer to form a first opening in the material layer by using the exposed first portions of the HM mandrel and the second spacer as a sub-etch-mask.
    Type: Application
    Filed: March 17, 2016
    Publication date: September 21, 2017
    Inventors: Yung-Sung Yen, Ru-Gun Liu, Chieh Chih Huang